Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-9311986-B2
Application number	US-201414469072-A
Country	US
Kind code	B2
Filing date	Aug 26, 2014
Priority date	Feb 19, 2014
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

A semiconductor memory device includes a control signal generator suitable for generating a control signal corresponding to temperature information, a refresh controller suitable for enabling a refresh signal for a smart refresh operation at a predetermined moment in response to a refresh command signal and enabling the refresh signal for a normal refresh operation at a moment corresponding to the control signal in response to the refresh command signal, and a data storage suitable for storing a data and performing the smart refresh operation and the normal refresh operation in response to the refresh signal of the refresh controller.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a control signal generator suitable for generating a control signal corresponding to temperature information;
a refresh controller suitable for enabling a refresh signal for a smart refresh operation at a predetermined moment in response to a refresh command signal and enabling the refresh signal for a normal refresh operation at a moment corresponding to the control signal in response to the refresh command signal; and
a data storage suitable for storing a data and performing the smart refresh operation and the normal refresh operation in response to the refresh signal of the refresh controller.

2. The semiconductor memory device of claim 1 , wherein the number of times that the normal refresh operation is performed is controlled based on the temperature information.

3. The semiconductor memory device of claim 1 , wherein the refresh controller includes:
a counting block suitable for generating a counting signal by counting the refresh command signal;
a normal refresh control block suitable for generating a source refresh signal by reflecting the counting signal and the control signal into the refresh command signal;
a smart counting block suitable for generating a smart refresh enabling signal by controlling a maximum counting value based on the control signal and counting the source refresh signal by the maximum counting value; and
a refresh output block suitable for outputting the refresh signal corresponding to the smart refresh operation and the normal refresh operation in response to the source refresh signal and the smart refresh enabling signal.

4. The semiconductor memory device of claim 3 , wherein the normal refresh control block includes:
a decoding part suitable for decoding the counting signal; and
a selection and transmission part suitable for selectively outputting the refresh command signal as the source refresh signal in response to the control signal and an output signal of the decoding part.

5. The semiconductor memory device of claim 3 , wherein the smart counting block includes:
a shifting part suitable for performing a shifting operation on the smart refresh enabling signal in response to the source refresh signal; and
a path control part suitable for controlling a signal transmission path of the shifting part in response to the control signal.

6. The semiconductor memory device of claim 3 , wherein the normal refresh control block controls the number of times that the source refresh signal is enabled in response to the control signal.

7. The semiconductor memory device of claim 5 , wherein the path control part controls the number of times that the shifting operation is performed in response to the control signal.

8. A semiconductor memory system, comprising:
a controller suitable for controlling a refresh operation by generating successive refresh command signals during a refresh operation section and replacing at least one refresh command signal among the successive refresh command signals with another command signal in response to temperature information; and
a semiconductor memory device suitable for performing the refresh operation in response to the refresh command signal and performing an operation corresponding to the another command signal.

9. The semiconductor memory system of claim 8 , wherein the semiconductor memory device includes:
a control signal generator suitable for generating a control signal corresponding to the temperature information;
a refresh controller suitable for enabling a refresh signal for a smart refresh operation at a predetermined moment in response to the refresh command signal and enabling the refresh signal for a normal refresh operation at a moment corresponding to the control signal in response to the refresh command signal; and
a data storage suitable for storing a data and performing the smart refresh operation and the normal refresh operation in response to the refresh signal of the refresh controller.

10. The semiconductor memory system of claim 9 , wherein the refresh controller includes:
a smart counting block suitable for generating a smart refresh enabling signal by controlling a maximum counting value based on the control signal and counting the refresh command signal by the maximum counting value; and
a refresh output block suitable for outputting the refresh signal corresponding to the smart refresh operation and the normal refresh operation in response to the source refresh signal and the smart refresh enabling signal.

11. The semiconductor memory system of claim 8 , further comprising:
a circuit suitable for performing a corresponding operation in response to the another command signal.

12. The semiconductor memory system of claim 8 , wherein the number of times that the refresh operation is performed is controlled based on the temperature information.

13. The semiconductor memory system of claim 8 , wherein the refresh command signal is a signal corresponding to the normal refresh operation.

14. A method for operating a semiconductor memory system, comprising:
comparing a predetermined maximum number of times of a refresh operation during a refresh operation section with a number of times of a refresh operation to be performed;
replacing the refresh operation with another operation based on a comparison result; and
performing the refresh operation and the another operation.

15. The method of claim 14 , further comprising:
setting the number of times of the refresh operation is to be performed based on temperature information.

16. The method of claim 14 , wherein the replacing of the refresh operation with another operation based on the comparison result includes:
performing the refresh operation and the another operation by determining whether the refresh operation is performed; and
determining whether the refresh operation section ended.

17. The method of claim 14 , wherein the refresh operation includes a smart refresh operation which is performed at a predetermined moment.

Assignees

• Sk Hynix Inc

Inventors

• Kim Chang-Hyun
• Song Choung-Ki

Classifications

• G11C11/40626 Primary

  Temperature related aspects of refresh operations · CPC title

• G11C11/40615

  Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs · CPC title

• G11C7/02

  with means for avoiding parasitic signals · CPC title