Low-power high-performance clock path architecture
US-2024393824-A1 · Nov 28, 2024 · US
US9178683B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9178683-B2 |
| Application number | US-201213478744-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 23, 2012 |
| Priority date | May 23, 2012 |
| Publication date | Nov 3, 2015 |
| Grant date | Nov 3, 2015 |
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A dynamic and flexible architecture and methods for demodulation of high data-rate streams with high symbol-rates, such as in satellite communications systems or computer network communications systems, is provided. A data stream of a data transmission is received, the data stream corresponding to a plurality of data symbols. A plurality of data samples corresponding to each of the data symbols is generated. Further, one or more representative data samples, corresponding each of the data symbols, are generated based at least in part on timing control signals and the generated data samples for the respective data symbol. The generated data samples corresponding to each of the data symbols other than the representative data samples are dropped. The timing control signals are then adjusted based at least in part on the generated representative data samples.
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What is claimed is: 1. A method comprising: receiving a data stream of a data transmission, the data stream corresponding to a plurality of data symbols; generating a plurality of intermediate data samples corresponding to each of the data symbols; generating one or more representative data samples, corresponding to each of the data symbols, based at least in part on timing control signals and the intermediate data samples for the respective data symbol; dropping certain of…
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