Comparator circuits with local ramp buffering for a column-parallel single-slope adc

Patent metadata

Field	Value
Publication number	US-2016118992-A1
Application number	US-201414523179-A
Country	US
Kind code	A1
Filing date	Oct 24, 2014
Priority date	Oct 24, 2014
Publication date	Apr 28, 2016
Grant date	—

Abstract

A comparator circuit suitable for use in a column-parallel single-slope analog-to-digital converter comprises a comparator, an input voltage sampling switch, a sampling capacitor arranged to store a voltage which varies with an input voltage when the sampling switch is closed, and a local ramp buffer arranged to buffer a global voltage ramp applied at an input. The comparator circuit is arranged such that its output toggles when the buffered global voltage ramp exceeds the stored voltage. Both DC- and AC-coupled comparator embodiments are disclosed.

First claim

1 . A comparator circuit suitable for use in a column-parallel single-slope analog-to-digital converter, said comparator circuit comprising:
an input node; a comparator; an input voltage sampling switch coupled to said input node; a sampling capacitor arranged to store a voltage which varies with an input voltage applied to said input node when said sampling switch is closed; and a local ramp buffer having an associated input and arranged to buffer a global voltage ramp applied directly to said local ramp buffer's input; said comparator circuit arranged such that the output of said comparator toggles when said buffered global voltage ramp exceeds said stored voltage.

2 . The comparator circuit of claim 1 , wherein said stored voltage is applied at a first input terminal of said comparator and said buffered global voltage ramp is applied at said comparator's second input terminal.

3 . The comparator circuit of claim 2 , wherein said sampling capacitor is connected between said comparator's first input terminal and a circuit common point and said sampling switch is connected between said input voltage and said comparator's first input terminal.

4 . The comparator circuit of claim 3 , said comparator circuit arranged to receive timing signals which operate said sampling switch such that said voltage is stored on said sampling capacitor before said global voltage ramp starts to ramp.

5 . A comparator circuit suitable for use in a column-parallel single-slope analog-to-digital converter, said comparator circuit comprising:
an input node; a comparator; an input voltage sampling switch coupled to said input node; a sampling capacitor arranged to store a voltage which varies with an input voltage applied to said input node when said sampling switch is closed; and a local ramp buffer having an associated input and arranged to buffer a global voltage ramp applied at said local ramp buffer's input, said comparator circuit arranged such that the output of said comparator toggles when said buffered global voltage ramp exceeds said stored voltage; and circuitry arranged to apply a reset voltage to a first input terminal of said comparator; said sampling capacitor connected in series between said sampling switch and a second input terminal of said comparator; and said buffered global voltage ramp switchably connected to the junction of said sampling capacitor and said sampling switch.

6 . The comparator circuit of claim 5 , wherein said circuitry comprises:
a first reset switch arranged to apply said reset voltage to said comparator's second input terminal when closed; a second reset switch arranged to connect said comparator's second input terminal to said comparator's first input terminal when closed; and a reset capacitor connected between said comparator's first input terminal and a circuit common point.

7 . The comparator circuit of claim 6 , further comprising:
a voltage ramp switch connected to apply said buffered global voltage ramp to the junction of said sampling capacitor and said sampling switch when closed; said comparator circuit arranged to:
close said first and second reset switches to apply said reset voltage to said comparator's first and second input terminals;
close said sampling switch to apply said input voltage to said sampling capacitor;
open said first and second reset switches and said sampling switch; and
close said voltage ramp switch to apply said buffered global voltage ramp to the junction of said sampling capacitor and said sampling switch.

8 . The comparator circuit of claim 7 , wherein said step of opening said first and second reset switches and said sampling switch comprises opening said sampling switch after said first and second reset switches are opened.

9 . The comparator circuit of claim 5 , wherein said circuitry comprises a reset switch connected between said comparator's first and second input terminals, said reset voltage connected directly to said comparator's first input terminal.

10 . The comparator circuit of claim 9 , further comprising:
a voltage ramp switch connected to apply said buffered global voltage ramp to the junction of said sampling capacitor and said sampling switch when closed; said comparator circuit arranged to:
close said reset switch to apply said reset voltage to said comparator's second input terminal;
close said sampling switch to apply said input voltage to said sampling capacitor;
open said reset switch and said sampling switch; and
close said voltage ramp switch to apply said buffered global voltage ramp to the junction of said sampling capacitor and said sampling switch.

11 . The comparator circuit of claim 10 , wherein said step of opening said reset switch and said sampling switch comprises opening said sampling switch after said reset switch is opened.

12 . The comparator circuit of claim 5 , wherein said circuitry comprises:
a first reset switch arranged to apply said reset voltage to said second terminal when closed; a second reset switch connected between said comparator's first input terminal and the output of said comparator; and a reset capacitor connected between said comparator's first input terminal and a circuit common point.

13 . The comparator circuit of claim 12 , further comprising:
a voltage ramp switch connected to apply said buffered global voltage ramp to the junction of said sampling capacitor and said sampling switch when closed; said comparator circuit arranged to:
close said first reset switch to apply said reset voltage to said comparator's second input terminal;
close said second reset switch to connect the output of said comparator to said reset capacitor;
close said sampling switch to apply said input voltage to said sampling capacitor;
open said first and second reset switches and said sampling switch; and
close said voltage ramp switch to apply said buffered global voltage ramp to the junction of said sampling capacitor and said sampling switch.

14 . The comparator circuit of claim 13 , wherein said step of opening said first and second reset switches and said sampling switch comprises opening said sampling switch after said first and second reset switches are opened.

15 . The comparator circuit of claim 5 , further comprising a voltage ramp switch connected to apply said buffered global voltage ramp to the junction of said sampling capacitor and said sampling switch when closed;
said comparator circuit arranged to:
close said voltage ramp switch to apply said buffered global voltage ramp to the junction of said sampling capacitor and said sampling switch; and
open said voltage ramp switch when the output of said comparator toggles to indicate that said buffered global voltage ramp exceeds said stored voltage.

16 . The comparator circuit of claim 1 , wherein said local ramp buffer is a source follower circuit.

17 . The comparator circuit of claim 1 , wherein said local ramp buffer is a high-gain amplifier employing unity gain feedback.

18 . The comparator circuit of claim 1 , further comprising a global voltage ramp generator which generates said global voltage ramp.

19 . A comparator circuit suitable for use in a column-parallel single-slope analog-to-digital converter, said comparator circuit comprising:
an input node; a comparator; an input voltage sampling switch coupled to said input node; a sampling capacitor arranged to store a voltage which varies with an input voltage applied to said input node when said sampling switch is closed; a local ramp

Assignees

• Teledyne Scient & Imaging Llc

Inventors

• Milkov Mihail M

Classifications

• H03M1/1245 Primary

  Details of sampling arrangements or methods · CPC title

• H03K4/90

  Linearisation of ramp (modifying slopes of pulses H03K6/04; scanning distortion correction for television receivers H04N3/23); Synchronisation of pulses · CPC title

• H03M1/368

  having a single comparator per bit, e.g. of the folding type · CPC title

• H03K3/0233

  Bistable circuits · CPC title

• H03M1/002 Primary

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title