Offset compensation for sense amplifiers

Patent metadata

Field	Value
Publication number	US-2016118945-A1
Application number	US-201614990000-A
Country	US
Kind code	A1
Filing date	Jan 7, 2016
Priority date	Oct 13, 2010
Publication date	Apr 28, 2016
Grant date	—

Abstract

A sense amplifier includes a first transistor having a first gate, a second transistor having a second gate in series with the first transistor, a third transistor having a third gate, and a fourth transistor having a fourth gate in series with the third transistor. A first input node is coupled to the third gate and the fourth gate, a second input node is coupled to the first gate and the second gate, and a first compensation transistor is in series with the first and second transistors or the third and fourth transistors, the first compensation transistor having a first compensation bulk. The first compensation bulk receives a first compensation voltage to modify the first compensation threshold, the first compensation voltage having a value calculated to compensate for an offset associated with the first and second input nodes.

First claim

What is claimed is:

1 . A sense amplifier comprising:
a first transistor having a first gate; a second transistor in series with the first transistor, the second transistor having a second gate; a third transistor having a third gate; a fourth transistor in series with the third transistor, the fourth transistor having a fourth gate; a first input node coupled to the third gate and the fourth gate; a second input node coupled to the first gate and the second gate; and a first compensation transistor in series with the first transistor and the second transistor or the third transistor and the fourth transistor, the first compensation transistor having a first compensation bulk, wherein the sense amplifier is configured to have the first compensation bulk receive a first compensation voltage to modify a first compensation threshold, the first compensation voltage having a value calculated to compensate for an offset associated with the first input node and the second input node.

2 . The sense amplifier of claim 1 , wherein
the first compensation transistor is in series with the first transistor and the second transistor, and the sense amplifier circuit further comprises a second compensation transistor in series with the third transistor and the fourth transistor, the second compensation transistor having a second compensation bulk.

3 . The sense amplifier of claim 2 , wherein the sense amplifier circuit is configured to have the second compensation bulk receive a second compensation voltage different from the first compensation voltage.

4 . The sense amplifier of claim 1 , wherein the value calculated to compensate for the offset is based on an equation:
V TN =V TO +γ(√{square root over ( V SB +2φ F )}−√{square root over (2φ F )})
where V TN is the first compensation threshold, V TO is a threshold voltage of the first compensation transistor for zero substrate bias, γ is a body effect parameter, 2 φF is a surface potential, and V SB is a difference between zero substrate bias and the value calculated to compensate for the offset.

5 . The sense amplifier of claim 1 , wherein the first compensation transistor is a PMOS transistor.

6 . The sense amplifier of claim 1 , wherein the first compensation transistor is an NMOS transistor.

7 . A sense amplifier circuit comprising:
a sense amplifier, the sense amplifier comprising:
a first transistor having a first gate;
a second transistor in series with the first transistor, the second transistor having a second gate;
a third transistor having a third gate;
a fourth transistor in series with the third transistor, the fourth transistor having a fourth gate;
a first input node coupled to the third gate and the fourth gate;
a second input node coupled to the first gate and the second gate; and
a first compensation transistor in series with the first transistor and the second transistor or the third transistor and the fourth transistor, the first compensation transistor having a first compensation bulk; and
an offset circuit configured to supply a first compensation voltage to the first compensation bulk to modify a first compensation threshold, the first compensation voltage having a value calculated to compensate for an offset associated with the first input node and the second input node.

8 . The sense amplifier circuit of claim 7 , wherein the offset circuit comprises a pair of latched transistors, the first transistor of the pair of latched transistors is configured to pass the calculated value to the bulk of the first compensation transistor, and the second transistor of the pair of latched transistors is configured to pass a voltage value different from the calculated value to the bulk of the first compensation transistor.

9 . The sense amplifier circuit of claim 8 , wherein the offset circuit is configured to select between the calculated value and the different voltage value in response to a pair of activation signals.

10 . The sense amplifier circuit of claim 7 , wherein
the first compensation transistor is in series with the first transistor and the second transistor, and the sense amplifier further comprises a second compensation transistor in series with the third transistor and the fourth transistor, the second compensation transistor having a second compensation bulk.

11 . The sense amplifier circuit of claim 10 , wherein the offset circuit is configured to supply a second compensation voltage to the second compensation bulk, the second compensation voltage being different from the first compensation voltage.

12 . The sense amplifier circuit of claim 10 , further comprising a second offset circuit configured to supply a second compensation voltage to the second compensation bulk.

13 . The sense amplifier circuit of claim 7 , wherein the value calculated to compensate for the offset is based on an equation:
V TN =V TO +γ(√{square root over ( V SB +2φ F )}−√{square root over (2φ F )})
where V TN is the first compensation threshold, V TO is a threshold voltage of the first compensation transistor for zero substrate bias, γ is a body effect parameter, 2 φF is a surface potential, and V SB is a difference between zero substrate bias and the value calculated to compensate for the offset.

14 . The sense amplifier circuit of claim 7 , further comprising a built-in self-test (BIST) circuit configured to execute a test on the sense amplifier.

15 . A sense amplifier circuit comprising:
a first power node having a first voltage value; a second power node having a second voltage value different from the first voltage value; a sense amplifier, the sense amplifier comprising:
a first branch between the first power node and the second power node, the first branch comprising a first complementary transistor pair and a first input node between the transistors of the first complementary transistor pair;
a second branch between the first power node and the second power node, the second branch comprising a second complementary transistor pair and a second input node between the transistors of the second complementary transistor pair; and
a compensation transistor in the first branch or the second branch,
wherein the first input node is coupled to a gate of each transistor of the second complementary transistor pair and the second input node is coupled to a gate of each transistor of the first complementary transistor pair; and
an offset circuit configured to supply a compensation voltage to a bulk of the compensation transistor, the compensation voltage being selectable between the first voltage value and a compensation voltage value equal to the first voltage value increased or decreased by a re-offset voltage value.

16 . The sense amplifier circuit of claim 15 , wherein the offset circuit comprises a pair of latched transistors, the first transistor of the pair of latched transistors is configured to pass the first voltage value to the bulk of the compensation transistor, and the second transistor of the pair of latched transistors is configured to pass the compensation voltage value to the bulk of the compensation transistor.

17 . The sense amplifier circuit of claim 16 , wherein the offset circuit is configured to select between the first voltage value and the compensation voltage value in response to a pair of activation signals.

18 . The sense amplifier circuit of claim 16 , wherein a gate of the compensation transistor is configured to receive the second voltage value.

19 . The sense am

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Upputuri Bharath
• Sampigethaya Shreekanth

Classifications

• G11C7/065 Primary

  Differential amplifiers of latching type · CPC title

• G11C29/026

  in sense amplifiers · CPC title

• G01R27/02

  Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant (by measuring phase angle only G01R25/00) · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C29/02

  Detection or location of defective auxiliary circuits, e.g. defective refresh counters · CPC title