Integrated snubber in a single poly mosfet

Patent metadata

Field	Value
Publication number	US-2016118380-A1
Application number	US-201614987610-A
Country	US
Kind code	A1
Filing date	Jan 4, 2016
Priority date	Mar 11, 2013
Publication date	Apr 28, 2016
Grant date	—

Abstract

Aspects of the present disclosure describe MOSFET devices that have snubber circuits. The snubber circuits comprise one or more resistors with a dynamically controllable resistance that is controlled by changes to a gate and/or drain potentials of the one or more MOSFET structures during switching events.

First claim

What is claimed is:

1 . A transistor device, comprising:
one or more gated structures formed in a semiconductor substrate, wherein the one or more gated structures comprise one or more metal-oxide-semiconductor field effect transistor (MOSFET) structures each having a gate terminal, a drain terminal and a source terminal; a snubber circuit connected in parallel with the one or more gated structures, wherein the snubber circuit includes one or more resistors with a dynamically controllable resistance controlled by changes to a control a gate potential of the one or more gated structures during a switching event.

2 . The device of claim 1 , wherein the one or more resistors with the dynamically controllable resistance are formed above a gate electrode of one or more of the MOSFET structures.

3 . The device of claim 2 , wherein the one or more resistors are three terminal resistors, having a source terminal, a drain terminal, and a gate terminal, wherein the gate terminal is the gate electrode of one or more of the MOSFET structures.

4 . The device of claim 1 , wherein the one or more resistors with a dynamically controllable resistance are thin film transistor (TFT) MOSFETs.

5 . The device of claim 1 , wherein the one or more resistors with a dynamically controllable resistance are depletion MOSFETs.

6 . The device of claim 1 , wherein the one or more resistors with a dynamically controllable resistance are enhancement MOSFETs connected in parallel with a passive resistor.

7 . The device of claim 1 , wherein the one or more resistors with a dynamically controllable resistance are JFETs.

8 . A transistor device, comprising:
one or more gated structures formed in a semiconductor substrate, wherein the one or more gated structures comprise one or more metal-oxide-semiconductor field effect transistor (MOSFET) structures each having a gate terminal, a drain terminal and a source terminal; a snubber circuit connected in parallel with the one or more gated structures, wherein the snubber circuit includes one or more resistors with a dynamically controllable resistance controlled by changes to a control a drain potential of the one or more MOSFET structures during a switching event.

9 . The device of claim 8 , wherein the one or more resistors with the dynamically controllable resistance are formed in a termination region of the transistor device, wherein the semiconductor substrate in the termination region is maintained at the drain potential of the one or more MOSFET structures.

10 . The device of claim 9 , wherein the one or more resistors are three terminal resistors, having a source terminal, a drain terminal, and a gate terminal, wherein the gate terminal is the semiconductor substrate in the termination region that is maintained at the drain potential of the one or more MOSFET structures.

11 . The device of claim 8 , wherein one or more of the resistors with the dynamically controllable resistance is controlled by changes to both the drain potential of the one or more MOSFET structures during a switching event and by changes to a gate potential of the one or more MOSFET structures during a switching event, and wherein one or more of the resistors with the dynamically controllable resistance is controlled by changes to the drain potential of the one or more MOSFET structures during a switching event.

12 . The device of claim 11 , wherein one or more of the resistors controlled by the gate potential and one or more of the resistors controlled by the drain potential are connected in parallel with each other.

13 . The device of claim 11 , wherein one or more of the resistors controlled by the gate potential and one or more of the resistors controlled by the drain potential are connected in series with each other.

14 . The device of claim 8 , wherein the one or more resistors with a dynamically controllable resistance are thin film transistor (TFT) MOSFETs.

15 . The device of claim 8 , wherein the one or more resistors with a dynamically controllable resistance are depletion MOSFETs.

16 . The device of claim 8 , wherein the one or more resistors with a dynamically controllable resistance are enhancement MOSFETs connected in parallel with a passive resistor.

17 . The device of claim 8 , wherein the one or more resistors with a dynamically controllable resistance are JFETs.

Assignees

• Alpha & Omega Semiconductor

Inventors

• Lui Sik
• Pan Ji

Classifications

• H10D84/817

  Combinations of field-effect devices and resistors only · CPC title

• H02M1/34 Primary

  Snubber circuits · CPC title

• H10D30/665

  having edge termination structures · CPC title

• H10D1/66

  Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors · CPC title

• H10D84/141

  VDMOS having built-in components · CPC title