Data writing method and memory system

Patent metadata

Field	Value
Publication number	US-2016110286-A1
Application number	US-201514982353-A
Country	US
Kind code	A1
Filing date	Dec 29, 2015
Priority date	Jun 29, 2013
Publication date	Apr 21, 2016
Grant date	—

Abstract

A data writing method and a memory system are disclosed. The method is applied to a memory system including at least a memory controller and a memory device, and the method includes: receiving, by the memory controller, change information sent by a cache, wherein the change information is information that is generated after the cache divides a first to-be-written cache line cache line of a last level cache LLC into at least one data block and that is used to indicate whether data in each of the at least one data block is changed; for each changed data block in which data is changed, sending, by the memory controller according to the change information, a corresponding column address and corresponding data to the memory device; and for a data block in which data is not changed, skipping performing, by the memory controller according to the change information, a write.

First claim

What is claimed is:

1 . A memory data updating method applied to a computer system comprising a CPU, a memory controller and a memory device, wherein the CPU comprises a last level cache (LLC), the method comprising:
dividing, by the CPU, a first cache line of the last level cache into k data blocks according to a burst write size, each of the k data blocks having a size equal to a multiple of the burst write size, wherein the burst write size is determined by a data bus width of the memory device, k is an integer and 2≦k≦burst length (BL), BL being a number of burst writes required for the memory controller to write data of one cache line of the last level cache into the memory device; determining, by the CPU, update information of the first cache line, wherein the update information of the first cache line indicates an updating status for each of the k data blocks in the first cache line, and sending, by the CPU, the update information of the first cache line to the memory controller.

2 . The memory data updating method according to claim 1 , wherein the step of determining update information of the first cache line comprises:
receiving, by the CPU, data in a buffer that is to be written into the first cache line; creating a k-bits vector in a register, wherein each bit of the k-bits vector is to store the comparing result between the data that is to be written into a data block with data stored in the corresponding data block; for each data block in the first cache line, comparing, by the CPU, the data in the buffer that is to be written into the each data block with data stored in the each data block; and storing a comparison result for each data block into the bit corresponding to the data block in the k-bits vector in the register.

3 . The memory data updating method according to claim 2 , wherein the step of storing the comparison result comprises:
if the data that is to be written into the data block is the same as data stored in the data block, setting the bit corresponding to the data block in the k bits vector to 1; if the data that is to be written into the data block and data stored in the data block are the same, setting the bit corresponding to the data block in the k bits vector to 0.

4 . A memory data writing method applied to a computer system comprising a CPU, a memory controller and a memory device, wherein the CPU comprises a last level cache (LLC), the method comprising:
receiving, by the memory controller, update information of a first cache line in the last level cache and data of the first cache line sent by the CPU, wherein the update information of the first cache line indicates an updating status for each of k data blocks in the first cache line, wherein each of the k data blocks has a size equal to a multiple of a burst write size which is a size of a data block that equal to a memory data bus width, k is an integer and 2≦k≦burst length (BL), BL being a number of burst writes required by the memory controller to write data of one cache line into the memory device; selecting, by the memory controller, changed data blocks in the first cache line according to the update information of the first cache line in the last level cache; generating, by the memory controller, memory addresses of the changed data blocks of the first cache line in the last level cache, wherein each memory address comprises a row address and a column address of one changed data block; and sending, by the memory controller, the memory addresses corresponding to the changed data blocks and data corresponding to the changed data blocks of the first cache line to the memory device for storing.

5 . The method according to claim 4 , wherein if a sum of the size of the changed data blocks of the first cache line is less than a length of the first cache line,
generating, by the memory controller, memory addresses of changed data blocks in a second cache line, wherein each memory address comprises a row address and a column address of each changed data block in the second cache line; sending the memory addresses corresponding to the changed data blocks of the first cache line, data corresponding to the changed data blocks of the first cache line, the memory addresses corresponding to the changed data blocks of the second cache line and data corresponding to the changed data blocks of the second cache line to the memory device, wherein a sum of a size of the changed data blocks of the second cache line and the sum of the size of the changed data blocks of the first cache line is less than or equal to the length of the first cache line in the last level cache.

6 . The method according to claim 5 , wherein the row address of each changed data block in the second cache line and the row address of each changed data block in the first cache line are the same, and there is no read command for the same row address in the memory device.

7 . A computer system, which comprises a CPU and a memory system, wherein the CPU comprises a last level cache (LLC), and the memory system comprises a memory controller and a memory device, wherein:
the cache is configured to: divide a first cache line of the last level cache into k data blocks according to a burst write size, each of the k data blocks having a size equal to a multiple of the burst write size, wherein the burst write size is determined by a data bus width of the memory device, k is an integer, and 2≦k≦burst length (BL), BL being a number of burst writes required for the memory controller to write data of one cache line of the last level cache into the memory device; determine update information of the first cache line, wherein the update information of the first cache line indicates an updating status for each of the k data blocks in the first cache line, and send the update information of the first cache line to the memory controller; the memory controller is configured to: receive update information of the first cache line in the last level cache and data of the first cache line sent by the CPU, wherein the update information of the first cache line indicates an updating status for each of k data blocks in the first cache line, wherein each of the k data blocks has a size that equal to a multiple of a burst write size which is a size of a data block that equal to a memory data bus width, k is an integer, and 2≦k≦burst length (BL), BL being a number of burst writes required by the memory controller to write data of one cache line into the memory device; select changed data blocks in the first cache line according to the update information of the first cache line; generate memory addresses of the changed data blocks of the first cache line in the last level cache, wherein each memory address comprises a row address and a column address of one changed data block; and send the memory addresses corresponding to the changed data blocks and data corresponding to the changed data blocks of the first cache line to the memory device for storing; and the memory is configured to: receive the memory addresses corresponding to the changed data blocks and data corresponding to the changed data blocks of the first cache line, and perform writing, according to the memory addresses corresponding to the changed data blocks and the data corresponding to the changed data blocks, the data of the changed data blocks in the memory device.

8 . The computer system according to claim 7 , wherein the memory controller is configured to: if a sum of the size of the changed data blocks of the first cache line is less than a length of the first cache line,
generate memory addresses of changed data blocks in a second cache line, wherein each memory address comprises a row address and a column address of each changed data block in the s

Assignees

• Huawei Tech Co Ltd

Inventors

• Xia Fei
• Jiang Dejun
• Xiong Jin

Classifications

• G06F2212/283

  Plural cache memories · CPC title

• G06F12/0866

  for peripheral storage systems, e.g. disk cache · CPC title

• G06F2212/657

  Virtual address space management · CPC title

• G06F12/0879

  Burst mode · CPC title

• G06F12/109

  for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence) · CPC title