Overlaid erase block mapping

US2016110282A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016110282-A1
Application numberUS-201414518560-A
CountryUS
Kind codeA1
Filing dateOct 20, 2014
Priority dateOct 20, 2014
Publication dateApr 21, 2016
Grant date

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Abstract

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An overlaid erase block (EB) mapping scheme for a flash memory provides efficient wear-leveling and reduces mount operation latency. The overlaid EB mapping scheme maps a first type of EB onto one of a plurality of physical erase blocks, in a corresponding portion of the flash memory. The first type of EB includes a plurality of pointers. The overlaid EB mapping scheme also maps each of second and third types of EBs onto one of the physical EBs that is not mapped to the first type of EB. The second type of EBs store system management information and the third type of EBs store user data. When the flash memory is started up, the overlaid EB mapping scheme scans the corresponding portion to locate the first type of EB, locates the system EBs using the pointers, and locates the data EBs using the system management information.

First claim

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What is claimed is: 1 . A method comprising: mapping a first type of erase block (EB)., which includes a plurality of pointers, onto one of a plurality of physical EBs, in a corresponding portion of a memory; and mapping each of second and third types of EBs onto one of the physical EBs that is not mapped to the first type of EB, the second type of EBs storing system management information and the third type of EBs storing user data. 2 . The method of…

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What does patent US2016110282A1 cover?
An overlaid erase block (EB) mapping scheme for a flash memory provides efficient wear-leveling and reduces mount operation latency. The overlaid EB mapping scheme maps a first type of EB onto one of a plurality of physical erase blocks, in a corresponding portion of the flash memory. The first type of EB includes a plurality of pointers. The overlaid EB mapping scheme also maps each of second …
Who is the assignee on this patent?
Spansion Llc
What technology area does this patent fall under?
Primary CPC classification G06F12/0253. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Apr 21 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).