Compact High-Voltage Semiconductor Package

Patent metadata

Field	Value
Publication number	US-2016104697-A1
Application number	US-201514849178-A
Country	US
Kind code	A1
Filing date	Sep 9, 2015
Priority date	Oct 8, 2014
Publication date	Apr 14, 2016
Grant date	—

Abstract

There are disclosed herein various implementations of a compact high-voltage semiconductor package. In one exemplary implementation, such a semiconductor package includes a power transistor, as well as a drain contact, a source contact, and a gate contact to provide external connections to the power transistor. The semiconductor package also includes a contour element formed between the drain contact and the source contact in the semiconductor package. The contour element increases a creepage distance between the drain contact and the source contact in the semiconductor package so as to increase a breakdown voltage of the semiconductor package.

First claim

1 . A semiconductor package comprising:
a power transistor; a drain contact, a source contact, and a gate contact to provide external connections to said power transistor; a contour element formed between said drain contact and said source contact in said semiconductor package; said contour element increasing a creepage distance between said drain contact and said source contact in said semiconductor package so as to increase a breakdown voltage of said semiconductor package.

2 . The semiconductor package of claim 1 , wherein said contour element is an elongated element traversing substantially an entire length of said semiconductor package.

3 . The semiconductor package of claim 1 , wherein said contour element comprises a groove formed in a packaging dielectric.

4 . The semiconductor package of claim 1 , wherein said contour element comprises a ridge in a packaging dielectric.

5 . The semiconductor package of claim 1 , wherein said power transistor is a composite field-effect transistor (FET) including a group IV FET cascaded with a high-voltage (HV) group III-V transistor.

6 . The semiconductor package of claim 5 , wherein said HV group III-V transistor is die stacked over said group IV FET.

7 . The semiconductor package of claim 5 , wherein a drain of said HV group III-V transistor is coupled to said drain contact, a source of said group IV FET is coupled to said source contact and to a gate of said HV group III-V transistor, and a gate of said group IV FET is coupled to said gate contact.

8 . The semiconductor package of claim 5 , wherein said group IV FET is a low-voltage (LV) silicon FET.

9 . The semiconductor package of claim 5 , wherein said HV group III-V transistor is a III-Nitride high electron mobility transistor (HEMT).

10 . The semiconductor package of claim 5 , wherein said semiconductor package comprises a quad flat no-lead (QFN) package having dimensions of less than 5 mm×5 mm.

11 . A semiconductor package comprising:
first and second power transistors; first and second drain contacts, first and second source contacts, and first and second gate contacts to provide respective external connections to said first and second power transistors; a first contour element formed between said first drain contact and said first source contact in said semiconductor package; a second contour element formed between said second drain contact and said second source contact in said semiconductor package; said first contour element increasing a first creepage distance between said first drain contact and said first source contact in said semiconductor package so as to increase a breakdown voltage of said semiconductor package; said second contour element increasing a second creepage distance between said second drain contact and said second source contact in said semiconductor package so as to increase said breakdown voltage of said semiconductor package.

12 . The semiconductor package of claim 11 , wherein at least one of said first contour element and said second contour element comprises a groove formed in a packaging dielectric.

13 . The semiconductor package of claim 11 , wherein at least one of said first contour element and said second contour element comprises a ridge in a packaging dielectric.

14 . The semiconductor package of claim 11 , wherein said first and second power transistors are composite field-effect transistors (FETs) each including a group IV FET cascoded with a high-voltage (HV) group III-V transistor.

15 . The semiconductor package of claim 11 , wherein said first and second power transistors are coupled to form a half bridge, said first power transistor being a high side switch and said second power transistor being a low side switch of said half bridge.

16 . A composite semiconductor package comprising:
a first semiconductor package housing a first power transistor joined with a second semiconductor package housing a second power transistor; a first contour element formed between a first drain contact and a first source contact in said first semiconductor package; a second contour element formed adjacent a second drain contact in said second semiconductor package; said first contour element increasing a first creepage distance between said first drain contact and said first source contact in said first semiconductor package so as to increase a breakdown voltage of said composite semiconductor package; said second contour element increasing a second creepage distance in said second semiconductor package so as to increase said breakdown voltage of said composite semiconductor package; said first contour element interfacing with and mechanically engaging said second contour element.

17 . The composite semiconductor package of claim 16 , wherein at least one of said first contour element and said second contour element comprises a groove formed in a packaging dielectric.

18 . The composite semiconductor package of claim 16 , wherein at least one of said first contour element and said second contour element comprises a ridge in a packaging dielectric.

19 . The composite semiconductor package of claim 16 , wherein said first and second power transistors are composite field-effect transistors (FETs) each including a group IV FET cascoded with a high-voltage (HV) group III-V transistor.

20 . The composite semiconductor package of claim 16 , wherein said first and second power transistors are electrically coupled so as to provide a bidirectional switch.

Assignees

• Int Rectifier Corp

Inventors

• Cho Eung San
• Cheah Chuan

Classifications

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/811

  Multiple chips on leadframes · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/111 Primary

  the semiconductor body being completely enclosed · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title