Driving chip and display device

Patent metadata

Field	Value
Publication number	US-2016104686-A1
Application number	US-201514787654-A
Country	US
Kind code	A1
Filing date	Mar 10, 2015
Priority date	Oct 11, 2014
Publication date	Apr 14, 2016
Grant date	—

Abstract

A driving chip and a display device, relating to the technical field of driving chip for displays, are disclosed. A surface of the driving chip has a first edge and a second edge opposite to each other. The driving chip includes connecting bumps and supporting bumps, which are arranged along the first edge to form at least one first bump column, and at either end of the first bump column, there is at least one of the supporting bumps; the connecting bumps and the supporting bumps are arranged along the second edge to form at least one second bump column, and at either end of the second bump column, there is at least one of the supporting bumps. A surface of the driving chip according to embodiments of the invention has bump columns, a supporting bump is disposed at an end of a bump column, and acts to support the driving chip favorably. Thus, upon bonding and packaging, the driving chip can bear a force in equilibrium as a whole, and occurrence of a problem of impression defectiveness is avoided.

First claim

1 . A driving chip, a surface of the driving chip having a first edge and a second edge opposite to each other, the driving chip comprising a plurality of connecting bumps and a plurality of supporting bumps, wherein,
the connecting bumps and the supporting bumps are arranged along the first edge to form at least one first bump column, and at either end of the first bump column, there is at least one of the supporting bumps; and the connecting bumps and the supporting bumps are arranged along the second edge to form at least one second bump column, and at either end of the second bump column, there is at least one of the supporting bumps.

2 . The driving chip claimed as claim 1 , wherein, the surface of the driving chip further includes a third edge and a fourth edge opposite to each other, the third edge and the fourth edge intersect with the first edge; and maximum distances between two ends of the first bump column and the second bump column and the third edge and the fourth edge are in a range of 4 to 200 μm.

3 . The driving chip claimed as claim 1 , wherein, a minimum distance between the first bump column and the second bump column is 60% to 70% of a distance between the first edge and the second edge.

4 . The driving chip claimed as claim 1 , wherein, a distance between the connecting bumps that are adjacent, between the connecting bumps and the supporting bumps that are adjacent, or between the supporting bumps that are adjacent is smaller than 200 μm.

5 . The driving chip claimed as claim 1 , wherein, the connecting bumps are input bumps or output bumps.

6 . The driving chip claimed as claim 1 , wherein, the surface of the driving chip further includes a third edge and a fourth edge opposite to each other, the third edge and the fourth edge intersect with the first edge; the connecting bumps and the supporting bumps are arranged along the third edge to form at least one third bump column, at either end of the third bump column, there is at least one of the supporting bumps; the connecting bumps and the supporting bumps are arranged along the fourth edge to form at least one fourth bump column, at either end of the fourth bump column, there is at least one of the supporting bumps.

7 . The driving chip claimed as claim 6 , wherein, maximum distances between two ends of the first bump column and the second bump column and the third edge and the fourth edge are in a range of 4 to 350 μm; maximum distances between two ends of the third bump column and the fourth bump column and the first edge and the second edge are in a range of 4 to 200 μm.

8 . The driving chip claimed as claim 6 , wherein, a minimum distance between the first bump column and the second bump column is 60% to 70% of a distance between the first edge and the second edge.

9 . The driving chip claimed as claim 6 , wherein, a distance between the connecting bumps that are adjacent, between the connecting bumps and the supporting bumps that are adjacent, or between the supporting bumps that are adjacent is smaller than 200 μm.

10 . The driving chip claimed as claim 6 , wherein, the connecting bumps are input bumps or output bumps.

11 . The driving chip claimed as claim 1 , wherein, lengths of the first edge and the second edge are larger than lengths of the third edge and the fourth edge.

12 . The driving chip claimed as claim 1 , wherein, a surface of the driving chip is in a shape of a rectangle.

13 . The driving chip claimed as claim 1 , wherein, at least one of the first bump column and the second bump column includes a plurality of bump columns parallel to each other.

14 . The driving chip claimed as claim 1 , wherein, thicknesses of the connecting bumps and the supporting bumps in a direction perpendicular to a surface of the driving chip are equal.

15 . A display device, comprising the driving chip claimed as claim 1 .

16 . The display device claimed as claim 15 , wherein, the surface of the driving chip further includes a third edge and a fourth edge opposite to each other, the third edge and the fourth edge intersect with the first edge; and maximum distances between two ends of the first bump column and the second bump column and the third edge and the fourth edge are in a range of 4 to 200 μm.

17 . The display device claimed as claim 15 , wherein, a minimum distance between the first bump column and the second bump column is 60% to 70% of a distance between the first edge and the second edge.

18 . The display device claimed as claim 15 , wherein, a distance between the connecting bumps that are adjacent, between the connecting bumps and the supporting bumps that are adjacent, or between the supporting bumps that are adjacent is smaller than 200 μm.

19 . The display device claimed as claim 15 , wherein, the connecting bumps are input bumps or output bumps.

20 . The display device claimed as claim 15 , wherein, the surface of the driving chip further includes a third edge and a fourth edge opposite to each other, the third edge and the fourth edge intersect with the first edge; the connecting bumps and the supporting bumps are arranged along the third edge to form at least one third bump column, at either end of the third bump column, there is at least one of the supporting bumps; the connecting bumps and the supporting bumps are arranged along the fourth edge to form at least one fourth bump column, at either end of the fourth bump column, there is at least one of the supporting bumps.

Assignees

• Boe Technology Group Co Ltd
• Hefei Boe Optoelectronics Tech

Inventors

• Cheng Liang
• Qi Peng
• Zheng Lu

Classifications

• H10W72/248

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/20 Primary

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H01L2924/15788

  Electricity · mapped topic

• H01L2924/12041

  Electricity · mapped topic

• H01L24/17 Primary

  Electricity · mapped topic