Method for manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-2016071952-A1
Application number	US-201514725666-A
Country	US
Kind code	A1
Filing date	May 29, 2015
Priority date	Sep 6, 2014
Publication date	Mar 10, 2016
Grant date	—

Abstract

A method for manufacturing a semiconductor device is provided. The method includes forming, on a substrate, a plurality of fins extending along a first direction; forming, on the fins, a dummy gate stack extending along a second direction; forming a gate spacer on opposite sides of the dummy gate stack in the first direction; epitaxially growing raised source/drain regions on the top of the fins on opposite sides of the gate spacer in the first direction; performing lightly-doping ion implantation through the raised source/drain regions with the gate spacer as a mask, to form source/drain extension regions in the fins on opposite sides of the gate spacer in the first direction; removing the dummy gate stack to form a gate trench; and forming a gate stack in the gate trench.

First claim

What is claimed:

1 . A method for manufacturing a semiconductor device, comprising the steps of:
forming, on a substrate, a plurality of fins extending along a first direction; forming, on the fins, a dummy gate stack extending along a second direction; forming a gate spacer on opposite sides of the dummy gate stack in the first direction; epitaxially growing raised source/drain regions on the top of the fins on opposite sides of the gate spacer in the first direction; performing lightly-doping ion implantation through the raised source/drain regions with the gate spacer as a mask, to form source/drain extension regions in the fins on opposite sides of the gate spacer in the first direction; removing the dummy gate stack to form a gate trench; and forming a gate stack in the gate trench.

2 . The method according to claim 1 , wherein before forming the dummy gate stack, the method further comprises the step of performing ion implantation to form a punch-through stop layer in the middle of the fins.

3 . The method according to claim 1 , wherein before forming the dummy gate stack, the method further comprises performing ion implantation to form a punch-through stop layer at the bottom of the fins.

4 . The method according to claim 1 , wherein before forming the dummy gate stack, the method further comprises performing ion implantation to form a punch-through stop layer in the middle and at the bottom of the fins.

5 . The method according to claim 1 , wherein the gate spacer comprises a first horizontal portion and a second vertical portion.

6 . The method according to claim 1 , wherein the lightly-doping ion implantation has implantation energy of 150-500 KeV.

7 . The method according to claim 1 , wherein the lightly-doping ion implantation has an implantation dosage of 10 14 -10 17 /cm 2 .

8 . The method according to claim 1 , wherein the lightly-doping ion implantation has implantation energy of 150-500 KeV and an implantation dosage of 10 14 -10 17 /cm 2 .

9 . The method according to claim 1 , wherein the lightly-doping ion implantation has 1-5% increase in implantation energy with every 1% increase in thickness of the raised source/drain region.

10 . The method according to claim 1 , wherein the lightly-doping ion implantation has 1.5% increase in implantation dosage with every 1% increase in thickness of the raised source/drain regions.

11 . The method according to claim 1 , wherein the lightly-doping ion implantation has 1-5% increase in implantation energy and implantation dosage with every 1% increase in thickness of the raised source/drain regions.

12 . The method according to claim 1 , wherein the lightly-doping ion implantation comprises multiple sub-steps with different process parameters, to form a junction depth distribution in a curve profile.

13 . The method according to claim 1 , wherein the lightly-doping ion implantation comprises multiple sub-steps with different process parameters, to form a junction depth distribution with a graded variation.

14 . The method according to claim 1 , wherein in performing the lightly-doping ion implantation, a horizontal tilt angle is adjusted to control a junction depth of the source/drain extension regions in the first direction.

15 . The method according to claim 1 , wherein before forming the gate trench, the method further comprises the steps of:
forming a second gate spacer on the gate spacer; performing heavily-doping ion implantation with the second gate spacer as a mask, to adjust a doping type and/or a doping concentration of the raised source/drain regions; and performing annealing to activate doped ions and/or repairing damages due to the ion implantation.

16 . The method according to claim 15 , wherein after performing annealing, the method further comprises the step of forming a contact etching stop layer and an inter-layer dielectric layer on the device.

17 . The method according to claim 1 , wherein the gate stack comprises a gate insulating layer of a high-K material and a gate conductive layer of a metal material.

Assignees

• Inst Of Microelectronics Cas

Inventors

• Yin Huaxiang
• Qin Changliang
• Ma Xiaolong
• Wang Guilei
• Zhu Huilong

Classifications

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D30/0243

  using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability · CPC title