Induced thermal gradients

Patent metadata

Field	Value
Publication number	US-2016055901-A1
Application number	US-201514838994-A
Country	US
Kind code	A1
Filing date	Aug 28, 2015
Priority date	Mar 31, 2011
Publication date	Feb 25, 2016
Grant date	—

Abstract

A temperature difference between a first thermal sensor and a second thermal sensor on a first die is determined. The temperature difference is transmitted from the first die to a circuit on a second die. A temperature from a thermal sensor on the second die is determined. The temperature difference and the temperature from the thermal sensor are utilized on the second die to modify operational characteristics of one or more circuits on the second die.

First claim

1 . An apparatus comprising:
a memory die including dynamic random access memory (DRAM), a mode register including a storage location for a thermal offset bit, and a memory thermal sensor; and a second die including logic circuitry thermally coupled with the memory die, the second die further including a first thermal sensor and a second thermal sensor, the first and second thermal sensors to detect a thermal gradient, and the logic circuitry to provide a thermal offset bit to the storage location for the thermal offset bit of the mode register on the memory die responsive to detection of a change in the thermal gradient, the memory thermal sensor of the memory die being aligned with or in close proximity with the first thermal sensor of the second die, and the second thermal sensor of the second die being located at a hot spot of the second die; wherein the memory die includes a temperature compensated self-refresh (TCSR) logic, the TCSR logic to modify a self-refresh rate of the DRAM responsive, at least in part, to the thermal offset bit.

2 . The apparatus of claim 1 , wherein a location of the memory thermal sensor in relation to the first sensor is to allow utilization of temperature information from the first thermal sensor with temperature information from the memory thermal sensor.

3 . The apparatus of claim 1 , wherein a value of the thermal offset bit is to represent a temperature range for the thermal gradient.

4 . The apparatus of claim 1 , wherein the thermal offset bit is to control refresh behavior for a plurality of channels of the memory die.

5 . The apparatus of claim 1 , wherein the second die comprises a processor core or graphics processor.

6 . The apparatus of claim 1 , wherein the second die comprises a system on a chip (SoC).

7 . The apparatus of claim 1 , further comprising:
one or more processors communicatively coupled to the logic circuitry; a network interface communicatively coupled with at least one of the one or more processors; and a display communicatively coupled with at least one of the one or more processors.

8 . A semiconductor die comprising:
a first thermal sensor and a second thermal sensor, the first and second thermal sensors to detect a thermal gradient; and logic circuitry to provide a thermal offset bit to a storage location for the thermal offset bit of a mode register of a memory die responsive to detection of a change in the thermal gradient; wherein the thermal offset bit is to direct a temperature compensated self-refresh (TCSR) logic of the memory die to modify a self-refresh rate of the DRAM; wherein the first thermal sensor is to be aligned with or in close proximity with a memory thermal sensor of the memory die, and wherein the second thermal sensor of the semiconductor die is located at a hot spot of the semiconductor die.

9 . The semiconductor die of claim 8 , wherein a location of the memory thermal sensor in relation to the first thermal sensor is to allow utilization of temperature information from the first thermal sensor with temperature information from the memory thermal sensor.

10 . The semiconductor die of claim 8 , wherein the semiconductor die is to be thermally coupled with the memory die.

11 . The semiconductor die of claim 8 , wherein a value of the thermal offset bit is to represent a temperature range for the thermal gradient.

12 . The semiconductor die of claim 8 , wherein the thermal offset bit is to control refresh behavior for a plurality of channels of the memory die.

13 . The semiconductor die of claim 8 , wherein the semiconductor die comprises a processor core or graphics processor.

14 . The semiconductor die of claim 8 , wherein the semiconductor die comprises a system on a chip (SoC).

15 . A memory die comprising:
dynamic random access memory (DRAM); a mode register including a storage location for a thermal offset bit; a memory thermal sensor; and a temperature compensated self-refresh (TCSR) logic, the TCSR logic to modify a self-refresh rate of the DRAM responsive, at least in part, to the thermal offset bit; and wherein the mode register is to receive the thermal offset bit from a second die responsive to a change in a thermal gradient between a first thermal sensor and a second thermal sensor of the second die, wherein the memory thermal sensor is to be aligned with or in close proximity with the first thermal sensor, and wherein the second thermal sensor is located at a hot spot of the second die.

15 . (canceled)

16 . The memory die of claim 15 , wherein the memory die is to be thermally coupled with the second die.

17 . The memory die of claim 15 , wherein a value of the thermal offset bit is to represent a temperature range for the thermal gradient.

18 . The memory die of claim 15 , further comprising a plurality of channels, wherein the thermal offset bit is to control refresh behavior for the plurality of channels.

19 . The memory die of claim 15 , wherein the second die comprises a processor core or graphics processor.

20 . The memory die of claim 15 , wherein the second die comprises a system on a chip (SoC).

21 . A method comprising:
detecting a thermal gradient with a first thermal sensor and a second thermal sensor of a semiconductor die; generating by logic circuitry of the semiconductor die a thermal offset bit responsive to detection of a change in the thermal gradient; and transmitting the thermal offset bit for storage in a storage location of a mode register of a memory die, the memory die including dynamic random access memory (DRAM); wherein the thermal offset bit is to direct a temperature compensated self-refresh (TCSR) logic of the memory die to modify a self-refresh rate of the DRAM; wherein the first thermal sensor is to be aligned with or in close proximity with a memory thermal sensor of the memory die, and the second thermal sensor is located at a hot spot of the semiconductor die.

22 . The method of claim 21 , wherein a location of the memory thermal sensor in relation to the first thermal sensor is to allow utilization of temperature information from the first thermal sensor with temperature information from the memory thermal sensor.

23 . The method of claim 21 , wherein the semiconductor die is to be thermally coupled with the memory die.

24 . The method of claim 21 , wherein a value of the thermal offset bit is to represent a temperature range for the thermal gradient.

25 . The method of claim 21 , wherein the thermal offset bit is to control refresh behavior for a plurality of channels of the memory die.

26 . At least one non-transitory computer-readable storage medium having stored thereon data representing sequences of instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:
detecting a thermal gradient with a first thermal sensor and a second thermal sensor of a semiconductor die; generating by logic circuitry of the semiconductor die a thermal offset bit responsive to detection of a change in the thermal gradient; and transmitting the thermal offset bit for storage in a storage location of a mode register of a memory die, the memory die including dynamic random access memory (DRAM); wherein the thermal offset bit is to direct a temperature compensated self-refresh (TCSR) logic of the memory die to modify a self-refresh rat

Assignees

• Intel Corp

Inventors

• Shoemaker Kenneth D

Classifications

• H10W90/752

  between stacked chips · CPC title

• G11C11/40615

  Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs · CPC title

• G11C11/40626 Primary

  Temperature related aspects of refresh operations · CPC title

• G11C2211/4067

  Refresh in standby or low power modes · CPC title

• G06F1/3275

  Power saving in memory, e.g. RAM, cache · CPC title