Semiconductor structure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2016027684-A1
Application number	US-201414337562-A
Country	US
Kind code	A1
Filing date	Jul 22, 2014
Priority date	Jul 22, 2014
Publication date	Jan 28, 2016
Grant date	—

Abstract

A semiconductor structure includes a semiconductor substrate and a shallow trench isolation (STI). The STI includes a sidewall interfacing with the semiconductor substrate. The STI extrudes from a bottom portion of the semiconductor substrate, and the STI includes a bottom surface contacting the bottom portion of the semiconductor substrate; a top surface opposite to the bottom surface. The bottom surface includes a width greater than a width of the top surface.

First claim

What is claimed is:

1 . A semiconductor structure, comprising:
a semiconductor substrate; and a shallow trench isolation (STI) including a sidewall interfacing with the semiconductor substrate, wherein the STI extrudes from a bottom portion of the semiconductor substrate, and the STI comprises:
a bottom surface contacting the bottom portion of the semiconductor substrate;
a top surface opposite to the bottom surface; and
a turning point whereby the STI is divided into an upper portion and a lower portion,
wherein the bottom surface comprises a width greater than a width of the top surface, and the sidewall has an inclined or curved surface along the upper portion.

2 . The semiconductor structure of claim 1 , wherein a width of the STI gradually becomes greater from the top surface to the bottom surface.

3 . (canceled)

4 . The semiconductor structure of claim 2 , wherein the sidewall of the STI is a curved surface.

5 . The semiconductor structure of claim 1 , wherein a width of the lower portion becomes greater from the turning point to the bottom surface.

6 . (canceled)

7 . The semiconductor structure of claim 5 , wherein the sidewall of the lower portion is a curved surface.

8 . The semiconductor structure of claim 1 , wherein a width at the turning point is greater than the width of the top surface, and the width of the bottom surface is greater than the width at the turning point.

9 . The semiconductor structure of claim 1 , wherein the sidewall comprises a protrusion adjacent to the bottom surface.

10 . The semiconductor structure of claim 1 , wherein the sidewall comprises at least two turning points where the STI comprises different widths at each turning point.

11 . The semiconductor structure of claim 1 , wherein the semiconductor substrate further comprises a fin structure interfacing with the sidewall of the STI, the fin structure further comprising:
a top surface including a width, wherein the top surface is higher than the top surface of the STI; and a bottom width at a horizontal level of the bottom portion of the semiconductor substrate, wherein the width of the top surface is greater than the bottom width.

12 . The semiconductor structure of claim 11 , further comprising:
a gate dielectric layer on the top surface and sidewalls of the fin structure; and a gate electrode over the gate dielectric layer.

13 . A semiconductor structure, comprising:
a semiconductor substrate comprising a first region and a second region, wherein the first region includes a fine pitch of active regions and the second region includes a coarse pitch of active regions; a first shallow trench isolation (STI) in the first region including a sidewall interfacing with the semiconductor substrate, wherein the first STI extrudes from a bottom portion of the semiconductor substrate, and the first STI comprises:
a bottom surface contacting the bottom portion of the semiconductor substrate;
a top surface opposite to the bottom surface,
wherein the bottom surface comprises a width greater than a width of the top surface; and
a second shallow trench isolation (STI) in the second region including a sidewall interfacing with the semiconductor substrate, wherein the second STI extrudes from a bottom portion of the semiconductor substrate, and the second STI comprises:
a bottom surface contacting the bottom portion of the semiconductor substrate;
a top surface opposite to the bottom surface,
wherein the bottom surface comprises a width greater than a width of the top surface,
wherein one of the first STI and the second STI comprises a turning point whereby the one of the first STI and the second STI is divided into an upper portion and a lower portion, and the sidewall of the one of the first STI and the second STI has an inclined or curved surface along the upper portion.

14 . The semiconductor structure of claim 13 , wherein a width of the lower portion becomes greater from the turning point to the bottom surface of the first STI.

15 . The semiconductor structure of claim 13 , wherein a width of the lower portion becomes greater from the turning point to the bottom surface of the second STI.

16 . The semiconductor structure of claim 13 , wherein the width of the top surface of the second STI is greater than the width of the top surface of the first STI.

17 . The semiconductor structure of claim 13 , wherein the bottom surface of the first STI is substantially equal to the horizontal level of the bottom surface of the second STI.

18 . The semiconductor structure of claim 13 , further comprising:
a gate structure on the semiconductor substrate, the first STI and the second STI, wherein the gate structure extends from the first region to the second region.

19 . (canceled)

20 . (canceled)

21 . A semiconductor structure, comprising:
a semiconductor substrate comprising a fin structure; and a shallow trench isolation (STI) including a sidewall interfacing with the fin structure, the fin structure further comprising:
a top surface including a width, wherein the top surface is higher than the top surface of the STI; and
a bottom width at a horizontal level of a bottom portion of the semiconductor substrate,
wherein the width of the top surface is greater than the bottom width, and the sidewall is a curved surface from the top surface to the bottom surface.

22 . The semiconductor structure of claim 21 , wherein the sidewall of the STI is a curved surface.

23 . The semiconductor structure of claim 21 , wherein the STI comprises:
a bottom surface contacting the bottom portion of the semiconductor substrate; and a top surface opposite to the bottom surface, wherein the bottom surface comprises a width greater than a width of the top surface.

24 . The semiconductor structure of claim 23 , wherein a width of the lower portion becomes greater from the turning point to the bottom surface.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Chang Che-Cheng
• Cheng Tung-Wen
• Hseih Jui Fu
• Lin Mu-Tsang

Classifications

• H10W10/0145

  of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence) · CPC title

• H10W10/0147

  the shapes being altered by a local oxidation of silicon process, e.g. trench corner rounding by LOCOS · CPC title

• H10W10/17 Primary

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/0151

  Manufacturing their isolation regions · CPC title