Selective die electrical insulation by additive process

Patent metadata

Field	Value
Publication number	US-2016020188-A1
Application number	US-201514868090-A
Country	US
Kind code	A1
Filing date	Sep 28, 2015
Priority date	Oct 27, 2009
Publication date	Jan 21, 2016
Grant date	—

Abstract

Additive processes are employed for electrically insulating selected surface regions on a stack of die; and methods for electrically interconnecting die in a stack of die, include additive processes for electrically insulating selected surface regions of the die. Regions that are not insulated according to the invention are available for electrical connection using electrically conductive material applied in flowable form to make electrically conductive traces.

First claim

1 . A method for electrically insulating at least a selected region of a die by selectively applying a dielectric material onto the selected region of the die.

2 . The method of claim 1 wherein the selected region of the die includes an interconnect pad, comprising selectively applying the dielectric material onto at least a portion of the interconnect pad.

3 . The method of claim 1 wherein the selected region of the die includes a selected region of a die sidewall, comprising selectively applying the dielectric material onto the selected region of the die sidewall surface.

4 . The method of claim 1 wherein the selected region of the die includes a selected area of the front side of the die, comprising selectively applying the dielectric material onto the selected area of the front side of the die.

5 . The method of claim 1 wherein the selected region of the die includes a selected area inboard of an interconnect pad, comprising selectively applying the dielectric material onto the selected area inboard of the interconnect pad.

6 . The method of claim 1 wherein the selected region of the die includes a selected area of an interconnect margin of the die, comprising selectively applying the dielectric material onto the selected area of the interconnect margin.

7 . The method of claim 1 wherein the selected region of the die includes a selected area adjacent an interconnect edge of the die, comprising selectively applying the dielectric material onto the selected area adjacent the interconnect edge.

8 . The method of claim 1 wherein the selected region of the die includes a selected area between interconnect pads in a row of pads on the die, comprising selectively applying the dielectric material onto the selected area between interconnect pads.

9 . The method of claim 1 , further comprising forming a conformal electrically conductive trace contacting an interconnect pad and passing over an insulating region resulting from selectively applying the dielectric material over the selected region.

10 . The method of claim 1 wherein forming the electrically conductive trace comprises depositing an electrically conductive material in flowable form and subsequently curing the material to form the trace.

11 . The method of claim 9 wherein the dielectric material is characterized by having a surface at least partly nonwettable by the electrically conductive material.

12 . The method of claim 9 , further comprising treating the deposited dielectric material so that a surface thereof is at least partly nonwettable by the electrically conductive material.

13 . The method of claim 1 wherein applying the dielectric material includes directing an aerosolized electrically insulative material onto the selected region.

14 . The method of claim 1 wherein applying the dielectric material includes directing a curable electrically insulative material onto the selected region, further comprising curing the material.

15 . A method for forming a stacked die assembly, comprising providing semiconductor die having electrical interconnect pads arranged in an interconnect margin adjacent an interconnect die edge; stacking a plurality of said die such that the pads in successive die in the stack are arranged in columns; selectively applying electrically insulation over selected pads at which electrical connection is not desired; and forming electrically conductive traces over the columns.

16 . The method of claim 15 , wherein the plurality of said die are in an offset configuration in which successive die in the stack are offset at the interconnect die edge.

17 . A method for electrically insulating a selected surface region on a die, comprising an additive process for depositing a dielectric material onto the selected surface region.

18 - 25 . (canceled)

Assignees

• Invensas Corp

Inventors

• Leal Jeffrey S

Classifications

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W72/834

  Interconnections on sidewalls of chips · CPC title

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P14/6346

  using printing, e.g. ink-jet printing · CPC title

• H10P14/6342

  Liquid deposition, e.g. spin-coating, sol-gel techniques or spray coating · CPC title