Gate driving method and driving apparatus of a display panel and display apparatus

Patent metadata

Field	Value
Publication number	US-2016019853-A1
Application number	US-201414552812-A
Country	US
Kind code	A1
Filing date	Nov 25, 2014
Priority date	Jul 16, 2014
Publication date	Jan 21, 2016
Grant date	—

Abstract

The present disclosure discloses a gate driving method, a driving apparatus of a display panel and a display apparatus. The driving apparatus may be in two driving modes, i.e., a first mode and a second mode. In the first mode, due to a reduced number of gate lines to be driven when various frames of images are displayed, the power consumption can be reduced. In addition, due to the effect of persistence of vision of human eyes, better quality of display images can be ensured while reducing power consumption. In the second mode, as respective lines of gate lines are driven progressively when various frames of images are displayed, the display panel is enabled to have better quality of display images. By switching the driving apparatus between the first mode and second mode, a number of gate lines to be driven can be reduced so as to reduce power consumption.

First claim

1 . A driving apparatus of a display panel, comprising:
a first gate driver connected to a first trigger signal terminal, configured to drive odd lines of gate lines on the display panel; a second gate driver connected to a second trigger signal terminal, configured to drive even lines of gate lines on the display panel; a first gating control module, connected in series between the first trigger signal terminal and the first gate driver; and a second gating control module, connected in series between the second trigger signal terminal and the second gate driver; wherein the first gating control module and the second gating control module each comprises a mode control signal terminal configured to receive a mode control signal; wherein the first gating control module and the second gating control module are configured to respectively control the first gate driver and the second gate driver to drive in a first mode when the mode control signal is in a first state and to respectively control the first gate driver and the second gate driver to drive in a second mode when the mode control signal is in a second state; wherein, in the first mode, when odd frames of images are displayed, the odd lines of gate lines are driven sequentially by the first gate driver, and when even frames of images are displayed, the even lines of gate lines are driven sequentially by the second gate driver; or, when the odd frames of images are displayed, the even lines of gate lines are driven sequentially by the second gate driver, and when the even frames of images are displayed, the odd lines of gate lines are driven sequentially by the first gate driver; and wherein in the second mode, when various frames of images are displayed, respective lines of gate lines are driven progressively.

2 . The driving apparatus according to claim 1 ,
wherein the first gating control module further comprises a first gating clock signal terminal configured to receive a first gating clock signal; wherein the second gating control module further comprises a second gating clock signal terminal configured to receive a second gating clock signal; wherein when the mode control signal is in the first state:
the first gating control module transmits a first trigger signal transmitted by the first trigger signal terminal to the first gate driver to drive the odd lines of gate lines sequentially when the first gating clock signal is a valid signal; and
the second gating control module transmits a second trigger signal transmitted by the second trigger signal terminal to the second gate driver to drive the even lines of gate lines sequentially when the second gating clock signal is a valid signal;
wherein when the mode control signal is in the second state:
the first gating control module transmits the first trigger signal to the first gate driver to drive the odd lines of gate lines sequentially; and
the second gating control module transmits the second trigger signal to the second gate driver to drive the even lines of gate lines sequentially; and
wherein the first gating clock signal and the second gating clock signal have opposite phases and a same period which is a sum of a display time of two frame cycles.

3 . The driving apparatus according to claim 2 ,
wherein the first gating control module comprises a first Negated AND (NAND) gate, a second NAND gate, a first NOT gate and a second NOT gate; wherein the first NOT gate has:
an input terminal which is the first gating clock signal terminal of the first gating control module; and
an output terminal connected to a first input terminal of the first NAND gate;
wherein the first NAND gate has:
a second input terminal which is the mode control signal terminal of the first gating control module; and
an output terminal connected to a first input terminal of the second NAND gate;
wherein the second NAND gate has:
a second input terminal connected to the first trigger signal terminal; and
an output terminal connected to an input terminal of the second NOT gate; and
wherein the second NOT gate has an output terminal connected to the first gate driver.

4 . The driving apparatus according to claim 2 ,
wherein the first gating control module comprises a first transistor, a second transistor, and a third transistor; wherein the first transistor and the second transistor each has a gate which is the mode control signal terminal of the first gating control module and a source connected to the first trigger signal terminal; wherein the first transistor has a drain connected to a source of the third transistor; wherein the second transistor has a drain respectively connected to the first gate driver and a drain of the third transistor; wherein the third transistor has a gate which is the first gating clock signal terminal of the first gating control module; and wherein the first transistor is an N-type transistor, and the second transistor is a P-type transistor; or the first transistor is a P-type transistor, and the second transistor is an N-type transistor.

5 . The driving apparatus according to claim 3 ,
wherein the second gating control module comprises a third NAND gate, a fourth NAND gate, a third NOT gate and a fourth NOT gate; wherein the third NOT gate has;
an input terminal which is the second gating clock signal terminal of the second gating control module; and
an output terminal connected to a first input terminal of the third NAND gate;
wherein the third NAND gate has:
a second input terminal which is the mode control signal terminal of the second gating control module; and
an output terminal connected to a first input terminal of the fourth NAND gate;
wherein the fourth NAND gate has:
a second input terminal connected to the second trigger signal terminal; and
an output terminal connected to an input terminal of the fourth NOT gate; and
wherein the fourth NOT gate has an output terminal connected to the second gate driver.

6 . The driving apparatus according to claim 4 ,
wherein the second gating control module comprises a fourth transistor, a fifth transistor, and a sixth transistor, wherein the fourth transistor and the fifth transistor each has a gate which is the mode control signal terminal of the second gating control module and a source connected to the second trigger signal terminal; wherein the fourth transistor has a drain connected to a source of the sixth transistor; wherein the fifth transistor has a drain respectively connected to the second gate driver and a drain of the sixth transistor; wherein the sixth transistor has a gate which is the second gating clock signal terminal of the second gating control module; and wherein the fourth transistor is an N-type transistor, and the fifth transistor is a P-type transistor; or the fourth transistor is a P-type transistor, and the fifth transistor is an N-type transistor.

7 . The driving apparatus according to claim 6 , wherein both the third transistor and the sixth transistor are N-type transistors or P-type transistors.

8 . A display apparatus, comprising the driving apparatus according to claim 1 .

9 . A display apparatus, comprising the driving apparatus according to claim 2 .

10 . A display apparatus, comprising the driving apparatus according to claim 3 .

11 . A display apparatus, comprising the driving apparatus according to claim 4 .

12 . A display apparatus, comprising the driving apparatus according to claim 5 .

13 . A display apparatus, comprising the driving apparatus according to claim 6 .

14 . A display apparatus, comprising the driving apparatus according to claim 7

Assignees

• Boe Technology Group Co Ltd
• Chengdu Boe Optoelect Tech Co

Inventors

• Jiang Xue
• Li Xinghua
• He Wei

Classifications

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G3/3681 Primary

  suitable for passive matrices only · CPC title

• G09G2310/0213

  controlling the sequence of the scanning lines with respect to the patterns to be displayed, e.g. to save power · CPC title

• G09G3/3677 Primary

  suitable for active matrices only · CPC title