Liquid crystal drive circuit and liquid crystal drive circuit control method

Patent metadata

Field	Value
Publication number	US-9973192-B2
Application number	US-201715433189-A
Country	US
Kind code	B2
Filing date	Feb 15, 2017
Priority date	Mar 26, 2015
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

There is provided a semiconductor device including (1) a first power source section that includes a first power source output terminal and a second power source output terminal that output voltages at mutually different voltage levels, (2) a first output section that includes a first output stage switch that is provided between the first power source output terminal and a first voltage output terminal, and a second output stage switch that is provided between the second power source output terminal and the first power source output terminal, and (3) a controller that performs ON/OFF control of the first output stage switch and the second output stage switch such that both the first output stage switch and the second output stage switch are in an OFF state over a predetermined period encompassing a point in time when a signal level of the first signal switches.

First claim

What is claimed is:

1. A semiconductor device comprising:
an input terminal configured to receive as an input an inversion signal that transitions between a low level and a high level;
a timing regulation circuit configured to output a first output signal and a second output signal that transition between the low level and the high level, the timing regulation circuit configured to
shift the second output signal from the high level to the low level after shifting the first output signal from the high level to the low level, in a case in which the inversion signal transitions from the low level to the high level, and
shift the first output signal from the low level to the high level after having shifted the second output signal from the low level to the high level, in a case in which the inversion signal transitions from the high level to the low level; and

a voltage output section configured to receive the first output signal and the second output signal, and to output a first voltage and a second voltage that is lower than the first voltage.

2. The semiconductor device according to claim 1 , wherein the voltage output section is configured to change respective voltage levels of the first voltage and the second voltage according to a transition of the inversion signal between the low level and the high level.

3. A semiconductor apparatus comprising:
a plurality of segment electrodes and a plurality of common electrodes that are arrayed in a lattice formation;
a plurality of liquid crystal elements, each of which is disposed at each intersection portion of the segment electrodes and the common electrodes; and
the semiconductor device according to claim 1 that supplies voltages to each of the segment electrodes and the common electrodes.

Assignees

• Lapis Semiconductor Co Ltd

Inventors

• Yamashita Takashi

Classifications

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G3/3614

  Control of polarity reversal in general · CPC title

• G09G3/36 Primary

  using liquid crystals · CPC title

• G09G3/3681

  suitable for passive matrices only · CPC title

• G09G3/3692

  suitable for passive matrices only · CPC title