Microcontroller programmable system on a chip with programmable interconnect

Patent metadata

Field	Value
Publication number	US-2016019169-A1
Application number	US-201514866439-A
Country	US
Kind code	A1
Filing date	Sep 25, 2015
Priority date	Oct 26, 2000
Publication date	Jan 21, 2016
Grant date	—

Abstract

Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.

First claim

1 - 20 . (canceled)

21 . A programmable device, comprising:
reconfigurable analog circuitry; reconfigurable digital circuitry; a plurality of input/output (I/O) blocks; and a global mapping system configured to selectively couple the plurality of I/O blocks with analog functional units of the reconfigurable analog circuitry and with digital functional units of the reconfigurable digital circuitry.

22 . The programmable device of claim 21 , further comprising a system timing block configured to generate a plurality of time bases each provided to at least one of the reconfigurable analog circuitry and the reconfigurable digital circuitry.

23 . The programmable device of claim 22 , further comprising a programmable interconnect configured to distribute one or more of the plurality of time bases to the reconfigurable digital circuitry for implementing a universal asynchronous receiver transmitter (UART) function in the reconfigurable digital circuitry.

24 . The programmable device of claim 21 , wherein the global mapping system further comprises an input global mapping unit and an output global mapping unit.

25 . The programmable device of claim 21 , wherein each of the analog functional units comprises a parametric setting register configured to store a value representing an electrical signal characteristic.

26 . The programmable device of claim 21 , wherein the reconfigurable analog circuitry comprises:
one or more switched capacitor blocks; and one or more continuous time blocks, wherein for each continuous time block of the one or more continuous time blocks, the continuous time block is configured to generate an output reflecting changes in an analog signal that varies continuously over time and that is supplied as an input to the continuous time block.

27 . The programmable device of claim 21 , wherein the reconfigurable analog circuitry is reconfigurable to perform any of a plurality of analog functions, wherein each of the digital functional units comprises a plurality of selectable logic circuits, and wherein each of the digital functional units is reconfigurable to perform any of a plurality of predetermined digital functions.

28 . A method of operating a programmable device, comprising:
performing an analog function on an analog signal in reconfigurable analog circuitry of the programmable device; performing a digital function on a digital signal in reconfigurable digital circuitry of the programmable device; in a global mapping system, selectively coupling a plurality of I/O blocks of the programmable device with analog functional units of the reconfigurable analog circuitry and with digital functional units of the reconfigurable digital circuitry.

29 . The method of claim 28 , further comprising:
generating a plurality of time bases in a system timing block; and providing the plurality of time bases to at least one of the reconfigurable analog circuitry and the reconfigurable digital circuitry.

30 . The method of claim 29 , further comprising distributing one or more of the plurality of time bases via a programmable interconnect to the reconfigurable digital circuitry for implementing a universal asynchronous receiver transmitter (UART) function in the reconfigurable digital circuitry.

31 . The method of claim 28 , further comprising, for each analog functional unit of the analog functional units, storing a value representing an electrical signal characteristic in a parametric setting register of the analog functional unit.

32 . The method of claim 28 , further comprising reconfiguring the reconfigurable analog circuitry and the reconfigurable digital circuitry by transferring an instruction from a read-only memory (ROM) to the reconfigurable analog circuitry and the reconfigurable digital circuitry.

33 . The method of claim 28 , further comprising, in a continuous time block of the reconfigurable analog circuitry, generating an output reflecting changes in an analog signal that varies continuously over time and that is supplied as an input to the continuous time block.

34 . The method of claim 29 , further comprising:
reconfiguring the reconfigurable analog circuitry to perform each of a plurality of analog functions, and reconfiguring the reconfigurable digital circuitry to perform each of a plurality of digital functions.

35 . A programmable system, comprising:
a microprocessor; reconfigurable analog circuitry coupled with the microprocessor; reconfigurable digital circuitry coupled with the microprocessor; a plurality of input/output (I/O) blocks; and a global mapping system configured to selectively couple the plurality of I/O blocks with analog functional units of the reconfigurable analog circuitry and with digital functional units of the reconfigurable digital circuitry.

36 . The programmable system of claim 35 , wherein the microprocessor is configured to reconfigure the reconfigurable analog circuitry and the reconfigurable digital circuitry by transferring an instruction from a read-only memory (ROM) to the reconfigurable analog circuitry and the reconfigurable digital circuitry.

37 . The programmable system of claim 35 , further comprising a system timing block configured to generate a plurality of time bases provided to at least one of the reconfigurable analog circuitry and the reconfigurable digital circuitry.

38 . The programmable system of claim 35 , wherein the global mapping system is further configured to selectively couple any of the plurality of I/O blocks to the microprocessor.

39 . The programmable system of claim 35 , wherein the global mapping system is further configured to selectively couple any of the plurality of I/O blocks with a different functional unit of the analog functional units and the digital functional units for each of a plurality of clock cycles.

40 . The programmable system of claim 35 , wherein the reconfigurable digital circuitry comprises a plurality of digital functional units each comprising a plurality of selectable logic circuits, wherein each of the plurality of digital functional units is reconfigurable to perform any of a plurality of predetermined digital functions, wherein the reconfigurable analog circuitry is reconfigurable to perform any of a plurality of analog functions, and wherein the reconfigurable analog circuitry comprises:
one or more continuous time blocks, wherein for each continuous time block of the one or more continuous time blocks, the continuous time block is configured to generate an output reflecting changes in an analog signal that varies continuously over time and that is supplied as an input to the continuous time block, and one or more switched capacitor blocks.

Assignees

• Cypress Semiconductor Corp

Inventors

• Snyder Warren S

Classifications

• G06F13/102 Primary

  where the program performs an interfacing function, e.g. device driver (G06F13/105 takes precedence; contention policies within device drivers G06F9/4881; scheduling within device drivers G06F9/52) · CPC title

• G06F9/44505

  Configuring for program initiating, e.g. using registry, configuration files · CPC title

• H03H19/004

  Switched capacitor networks · CPC title

• G06F15/7817

  Specially adapted for signal processing, e.g. Harvard architectures · CPC title

• H03B5/32

  being a piezoelectric resonator (selection of piezoelectric material H10N30/00) · CPC title