Dynamic power limit sharing in a platform

Patent metadata

Field	Value
Publication number	US-2016018883-A1
Application number	US-201514867490-A
Country	US
Kind code	A1
Filing date	Sep 28, 2015
Priority date	Mar 29, 2012
Publication date	Jan 21, 2016
Grant date	—

Abstract

A method and apparatus for dynamic power limit sharing among the modules in the platform. In one embodiment of the invention, the platform comprises a processor and memory modules. By expanding the power domain to include the processor and the memory modules, dynamic sharing of the power budget of the platform between the processor and the memory modules is enabled. For low-bandwidth workloads, the dynamic sharing of the power budget offers significant opportunity for the processor to increase its frequency by using the headroom in the memory power and vice versa. This enables higher peak performance for the same total platform power budget in one embodiment of the invention.

First claim

What is claimed is:

1 . A processor comprising:
a plurality of cores, wherein at least a first core of the plurality of cores comprises a fetch logic to fetch instructions, a decode logic to decode the instructions, and execution logic to execute the instructions; a cache memory; and logic to:
dynamically set, for a platform comprising the processor and a memory module, a power limit for the processor and another power limit for the memory module based on a power budget for the platform, wherein the power limit for the processor is to be set to at least a minimum allowed power consumption of the processor;
analyze an average power consumption of the processor;
analyze another average power consumption of the memory module; and
adjust a power consumption of at least one of the processor and the memory module to enforce the power budget.

2 . The processor of claim 1 , wherein the logic is to set the power limit for the processor as a difference of the power budget for the platform and the another power limit for the memory module.

3 . The processor of claim 1 , wherein the logic is further to determine a time period to enforce the power budget for the platform, and to dynamically set the power limit for the processor and the another power limit for the memory module based on the power budget for the platform for a duration of the time period.

4 . The processor of claim 3 , further comprising a first storage to store the time period.

5 . The processor of claim 4 , further comprising a second storage to store the power budget for the platform.

6 . The processor of claim 1 , wherein the logic is to determine the power limit for the processor according to one or more of:
a number of stall counts of the processor; and characteristics of workloads executed by the processor.

7 . The processor of claim 1 , wherein the logic to determine the power limit for the memory module according to memory bandwidth utilization of the memory module.

8 . The processor of claim 1 , wherein the logic is to adjust the power consumption of the processor by adjustment of one or more of, a voltage, a frequency, instruction throughput, and a performance level of code, of the processor.

9 . The processor of claim 1 , wherein the logic is to adjust the power consumption of the memory module by adjustment of one or more of, read operations, write operations, and a voltage, of the memory module.

10 . The processor of claim 1 , wherein the processor further comprises a graphics processor.

11 . The processor of claim 1 , wherein the processor further comprises a power control unit.

12 . The processor of claim 1 , wherein the processor further comprises a memory controller.

13 . A system comprising:
a logic module; and a processor coupled with the logic module, to:
dynamically set, for the system, a power limit for the processor and another power limit for the logic module based on a power budget for the system, wherein the power limit for the processor is to be set to at least a minimum allowed power consumption of the processor;
analyze an average power consumption of the processor;
analyze another average power consumption of the logic module; and
adjust a power consumption of at least one of the processor and the logic module to enforce the power budget.

14 . The system of claim 13 , wherein the processor is further to determine a time period to enforce the power budget for the system, and to dynamically set the power limit for the processor and the another power limit for the logic module based on the power budget for the system for a duration of the time period.

15 . The system of claim 13 , wherein the processor is to adjust the power consumption of the processor according to one or more of adjustment of a voltage, a frequency, instruction throughput, and a performance level of code, of the processor.

16 . The system of claim 13 , wherein the processor is to determine the power limit for the logic module according to bandwidth utilization of the logic module.

17 . The system of claim 13 , wherein the logic module comprises one of a memory module, a graphics processor unit (GPU), and a co-processor.

18 . A non-transitory machine readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
dynamically setting, for a platform comprising a processor and a memory module, a power limit for the processor and another power limit for the memory module based on a power budget for the platform, wherein the power limit for the processor is to be set to at least a minimum allowed power consumption of the processor; analyzing an average power consumption of the processor; analyzing another average power consumption of the memory module; and adjusting a power consumption of at least one of the processor and the memory module to enforce the power budget.

19 . The non-transitory machine readable medium of claim 18 , wherein the method further comprises setting the power limit for the processor as a difference of the power budget for the platform and the another power limit for the memory module.

20 . The non-transitory machine readable medium of claim 18 , wherein the method further comprises determining the power limit for the processor according to one or more of:
a number of stall counts of the processor; and characteristics of workloads executed by the processor.

Assignees

• Intel Corp

Inventors

• Varma Ankush
• Sistla Krishnakanth V
• Quiroz Cesar A
• Garg Vivek
• Rowland Martin T
• Sodhi Inder M
• Burns James S

Classifications

• G06F1/3287 Primary

  by switching off individual functional units in the computer system · CPC title

• G06F1/3275

  Power saving in memory, e.g. RAM, cache · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F1/324 Primary

  by lowering clock frequency · CPC title

• G06F1/26

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title