Integrated circuit with multiple cells having different heights

Patent metadata

Field	Value
Publication number	US-2016013271-A1
Application number	US-201414328408-A
Country	US
Kind code	A1
Filing date	Jul 10, 2014
Priority date	Jul 10, 2014
Publication date	Jan 14, 2016
Grant date	—

Abstract

An integrated circuit comprises a first cell having first cell height and a first line routed at a first line height and having a first line width. The integrated circuit also comprises a second cell having a second cell height different from the first cell height and a second line routed at a second line height and a second line width different from the first line width. The integrated circuit further comprises a third cell. The third cell has a third line having a first end and a second end. The first end has a first end width. The second end has a second end width. The first end width is equal to the first line width. The second end width is equal to the second line width. The first end is coupled with the first line. The second end is coupled with the second line.

First claim

What is claimed is:

1 . An integrated circuit comprising:
a first cell having:
a first top surface and a first bottom surface, the first top surface separated from the first bottom surface by a first cell height; and
a first line routed at a first line height relative to the first bottom surface, the first line having a first line width;
a second cell having:
a second top surface and a second bottom surface, the second top surface separated from the second bottom surface by a second cell height different from the first cell height;
a second line routed at a second line height relative to the second bottom surface, the second line having a second line width different from the first line width; and
a third cell having:
a third line having a first end and a second end, the first end having a first end width, the second end having a second end width, the first end width being equal to the first line width, the second end width being equal to the second line width, the first end being coupled with the first line, and the second end being coupled with the second line.

2 . The integrated circuit of claim 1 , the third cell further comprising a third top surface and a third bottom surface, the third top surface being separated from the third bottom surface by a third cell height, and the third cell height being equal to the first cell height or the second cell height.

3 . The integrated circuit of claim 2 , wherein the third bottom surface is horizontally aligned with one or more of the first bottom surface or the second bottom surface.

4 . The integrated circuit of claim 2 , wherein
the first bottom surface, the second bottom surface, and the third bottom surface are horizontally misaligned, and the first top surface, the second top surface, and the third top surface are horizontally misaligned.

5 . The integrated circuit of claim 1 , wherein the first line height is equal to the first cell height or the second line height is equal to the second cell height.

6 . The integrated circuit of claim 1 , wherein the first line, the second line, and the third line are power lines or ground lines.

7 . The integrated circuit of claim 6 ,
the first cell further comprising a fourth line routed at a fourth line height relative to the first bottom surface, the fourth line having a fourth line width, the second cell further comprising a fifth line routed at a fifth line height relative to the second bottom surface, the fifth line having a fifth line width, the third cell further comprising a sixth line having a third end and a fourth end, the third end having a third end width, the fourth end having a fourth end width, the third end width being equal to the fourth line width, the fourth end width being equal to the fifth line width, the third end being coupled with the fourth line, and the fourth end being coupled with the fifth line, and the fourth line, the fifth line, and the sixth line are the other of power lines or ground lines.

8 . The integrated circuit of claim 6 , wherein the fourth line height is different from the fifth line height.

9 . The integrated circuit of claim 1 ,
the first cell further comprising a first doped region and a second doped region, the first doped region being separated from the second doped region by a first boundary, the first boundary having a first boundary height relative to the first bottom surface; the second cell further comprising a third doped region and a fourth doped region, the third doped region being separated from the fourth doped region by a second boundary, the second boundary having a second boundary height relative to the second bottom surface; and the third cell further comprising a fifth doped region and a sixth doped region, the fifth doped region being separated from the sixth doped region by a third boundary; the third boundary being horizontally aligned with the first boundary and the second boundary.

10 . The integrated circuit of claim 9 , wherein the first boundary height is equal to the second boundary height.

11 . The integrated circuit of claim 9 , wherein the first boundary height is different from the second boundary height, the third boundary has a first portion horizontally aligned with the first boundary, and the third boundary has a second portion horizontally aligned with the second boundary.

12 . The integrated circuit of claim 9 , wherein the third line is routed parallel to the third boundary.

13 . The integrated circuit of claim 1 , wherein the third line is routed having one of an S-shape, an L-shape, or a J-shape.

14 . The integrated circuit of claim 1 , wherein the third cell is between the first cell and the second cell, and the third cell abuts one or more of the first cell or the second cell.

15 . A method of designing an integrated circuit, the method comprising:
generating, by a processor, a first cell having:
a first top surface and a first bottom surface, the first top surface separated from the first bottom surface by a first cell height; and
a first line routed at a first line height relative to the first bottom surface, the first line having a first line width;
generating, by the processor, a second cell having:
a second top surface and a second bottom surface, the second top surface separated from the second bottom surface by a second cell height different from the first cell height;
a second line routed at a second line height relative to the second bottom surface, the second line having a second line width different from the first line width;
generating, by the processor, a third cell having:
a third line having a first end and a second end, the first end having a first end width, the second end having a second end width, the first end width being equal to the first line width, the second end width being equal to the second line width; and
coupling the first end with the first line, and the second end with the second line.

16 . The method of claim 15 , wherein the first line, the second line, and the third line are power lines or ground lines.

17 . The method of claim 16 , further comprising:
sandwiching the third cell between the first cell and the second cell, the third cell being sandwiched in direct contact with the first cell and the second cell.

18 . An integrated circuit comprising:
a first cell having:
a first top surface and a first bottom surface, the first top surface separated from the first bottom surface by a first cell height; and
a first line routed at the first cell height, the first line having a first line width;
a second cell having:
a second top surface and a second bottom surface, the second top surface separated from the second bottom surface by a second cell height different from the first cell height;
a second line routed at the second cell height, the second line having a second line width different from the first line width; and
a third cell having:
a third line having a first end and a second end, the first end having a first end width, the second end having a second end width, the first end width being equal to the first line width, the second end width being equal to the second line width, the first end being coupled with the first line, and the second end being coupled with the second line,
wherein the first line, the second line, and the third line are power lines or ground lines.

19 . The integrated circuit of claim 18 ,
the first cell further comprising a fourth line routed along the first bottom surface, the fourth line having a fourth

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Chiang Ting-Wei
• Tien Li-Chun
• Huang Ming-Jin
• Sue Pin-Dai

Classifications

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• H10D62/117 Primary

  Shapes of semiconductor bodies · CPC title

• G06F17/5072

  Physics · mapped topic