Selective removal of semiconductor fins

Patent metadata

Field	Value
Publication number	US-2016013183-A1
Application number	US-201414325547-A
Country	US
Kind code	A1
Filing date	Jul 8, 2014
Priority date	Jul 8, 2014
Publication date	Jan 14, 2016
Grant date	—

Abstract

An array of semiconductor fins is formed on a top surface of a substrate. A dielectric material liner is formed on the surfaces of the array of semiconductor fins. A photoresist layer is applied and patterned such that sidewalls of an opening in the photoresist layer are parallel to the lengthwise direction of the semiconductor fins, and are asymmetrically laterally offset from a lengthwise direction passing through the center of mass of a semiconductor fin to be subsequently removed. An angled ion implantation is performed to convert a top portion of dielectric material liner into a compound material portion. The compound material portion is removed selective to the remaining dielectric material liner, and the physically exposed semiconductor fin can be removed by an etch or converted into a dielectric material portion by a conversion process. The dielectric material liner can be removed after removal of the semiconductor fin.

First claim

What is claimed is:

1 . A semiconductor structure comprising:
a plurality of semiconductor fins located on a substrate, each of said plurality of semiconductor fins having a parallel pair of semiconductor sidewalls that are laterally spaced from each other by a uniform fin width; and a dielectric material portion having a parallel pair of dielectric sidewalls that are parallel to said parallel pairs of semiconductor sidewalls, wherein a bottom surface of said dielectric material portion adjoining said parallel pair of dielectric sidewalls has a same width as said uniform fin width.

2 . The semiconductor structure of claim 1 , wherein an upper sub-portion of said dielectric material portion has a greater width than said uniform fin width.

3 . The semiconductor structure of claim 1 , wherein said plurality of semiconductor fins includes at least two semiconductor fins that constitute a one-dimensional array having a uniform pitch along a direction perpendicular to said parallel pairs of semiconductor sidewalls, and a lateral distance between a semiconductor sidewall of one of said at least two semiconductor fins and one of said parallel pair of dielectric sidewalls is the same as said uniform pitch.

4 . The semiconductor structure of claim 1 , further comprising:
a gate dielectric contacting surfaces of said plurality of semiconductor fins and contacting surfaces of said dielectric material portion; and a gate electrode contacting said gate dielectric.

5 . The semiconductor structure of claim 1 , wherein a vertical cross-sectional shape of said dielectric material portion along a vertical plane perpendicular to said parallel pair of dielectric sidewalls is asymmetric.

6 . The semiconductor structure of claim 1 , wherein said dielectric material portion protrudes farther upward from a top surface of said substrate than a topmost portion of said plurality of semiconductor fins.

7 . The semiconductor structure of claim 1 , further comprising a shallow trench isolation layer laterally surrounding said dielectric material portion and a lower portion of each of said plurality of semiconductor fins.

8 . The semiconductor structure of claim 7 , wherein a topmost surface of said dielectric material portion is coplanar with a top surface of said shallow trench isolation layer.

9 . The semiconductor structure of claim 7 , wherein a bottommost surface of said dielectric material portion is vertically offset from a horizontal plane including a planar bottom surface of said shallow trench isolation layer.

10 . The semiconductor structure of claim 7 , further comprising a dielectric liner contacting a top surface of said substrate, lower portions of said parallel pairs of semiconductor sidewalls, and said parallel pair of dielectric sidewalls.

11 . The semiconductor structure of claim 7 , further comprising a semiconductor material portion having a width that is the same as said uniform fin width and a width of said dielectric material portion.

12 . The semiconductor structure of claim 7 , wherein said dielectric material portion extends below a top surface of said substrate and below a horizontal plane including a planar bottom surface of said shallow trench isolation layer.

13 . A method of forming a semiconductor structure comprising:
forming a plurality of semiconductor fins on a substrate; forming a material liner on physically exposed surfaces of said plurality of semiconductor fins and said substrate; applying and patterning a photoresist layer over said material liner, wherein at least a semiconductor fin is positioned between a pair of sidewalls of said patterned photoresist layer; implanting an implant material into a top portion of said material liner employing an angled implantation process, wherein a first sidewall portion of said material liner located on one side of said semiconductor fin and a top portion of said material liner are converted into an compound material portion, and said implant material is not implanted into a second sidewall portion of said material liner located on another side of semiconductor fin; and removing said compound material portion selective to remaining portions of said material liner that are not implanted with said implant material.

14 . The method of claim 13 , further comprising removing at least a portion of said semiconductor fin selective to said remaining portions of said material liner.

15 . The method of claim 13 , further comprising converting at least a portion of said semiconductor fin into a dielectric material portion, wherein said remaining portions of said material liner laterally surrounds said dielectric material portion.

16 . The method of claim 15 , wherein said dielectric material portion has a greater width at an upper portion than at a lower portion.

17 . The method of claim 15 , further comprising:
forming a gate dielectric on sidewalls of said plurality of semiconductor fins and surfaces of said dielectric material portion; and forming a gate electrode on said gate dielectric.

18 . The method of claim 13 , further comprising:
forming a cavity by recessing said semiconductor fin selective to said remaining portions of said material liner; and forming a dielectric material portion in said cavity by depositing a dielectric material in said cavity.

19 . The method of claim 13 , further comprising forming a shallow trench isolation layer on a portion of said material liner.

20 . The method of claim 13 , further comprising etching at least a region of said remaining portion of said material liner selective to said plurality of semiconductor fins.

Assignees

• IBM

Inventors

• Basker Veeraraghavan S
• Cheng Kangguo
• Khakifirooz Ali

Classifications

• H10P32/30

  Diffusion for doping of conductive or resistive layers · CPC title

• H10P30/40

  into insulating materials · CPC title

• H10P76/204

  of organic photoresist masks · CPC title

• H10P50/693

  characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane · CPC title

• H10P50/667

  by liquid etching only · CPC title