Methods of Packaging Semiconductor Devices and Packaged Semiconductor Devices

Patent metadata

Field	Value
Publication number	US-2016013152-A1
Application number	US-201414326228-A
Country	US
Kind code	A1
Filing date	Jul 8, 2014
Priority date	Jul 8, 2014
Publication date	Jan 14, 2016
Grant date	—

Abstract

Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming a dam structure on dies proximate edge regions of the dies. A molding material is disposed around the dies, and a top portion of the molding material and a top portion of the dam structure are removed.

First claim

1 . A method of packaging a semiconductor device, the method comprising:
forming a dam structure on a plurality of dies proximate edge regions of the plurality of dies; disposing a molding material around the plurality of dies; and removing a top portion of the molding material and a top portion of the dam structure.

2 . The method according to claim 1 , wherein removing the top portion of the molding material and the top portion of the dam structure comprises a grinding process or a chemical-mechanical polishing (CMP) process.

3 . The method according to claim 1 , wherein removing the top portion of the molding material comprises removing a portion of the molding material proximate the dam structure.

4 . The method according to claim 1 , further comprising forming an interconnect structure over the plurality of dies and the molding material.

5 . The method according to claim 4 , further comprising coupling a plurality of connectors to the interconnect structure.

6 . The method according to claim 4 , wherein forming the interconnect structure comprises forming fan-out regions.

7 . The method according to claim 4 , wherein forming the interconnect structure comprises forming a post-passivation interconnect (PPI) structure or a redistribution layer (RDL).

8 . A method of packaging a semiconductor device, the method comprising:
coupling a plurality of dies to a carrier; forming a dam structure on each of the plurality of dies proximate edge regions of the plurality of dies; disposing a molding material over the carrier around the plurality of dies; removing a top portion of the molding material and a top portion of the dam structure; forming an interconnect structure over the plurality of dies and the molding material; removing the carrier; and dicing the molding material and the interconnect structure to form a plurality of packaged semiconductor devices.

9 . The method according to claim 8 , wherein forming the dam structure is performed before coupling the plurality of dies to the carrier, or wherein forming the dam structure is performed after coupling the plurality of dies to the carrier.

10 . The method according to claim 8 , wherein forming the dam structure comprises a process selected from the group consisting essentially of an attachment process, a lithography process, a spin-on process, a deposition process, a lamination process, a process for forming a material layer of the plurality of dies, and combinations thereof.

11 . The method according to claim 8 , wherein each of the plurality of dies comprises a plurality of contact pads disposed thereon, the plurality of contact pads comprising a first height, and wherein forming the dam structure comprises forming a dam structure comprising a second height, the second height being greater than the first height.

12 . The method according to claim 11 , wherein removing the top portion of the dam structure comprises forming a dam structure comprising a third height, the third height being greater than or about the same as the first height.

13 - 20 . (canceled)

21 . A method of packaging a semiconductor device, the method comprising:
providing an integrated circuit die having a plurality of contact pads and a dam structure disposed thereon, the dam structure being disposed around the plurality of contact pads proximate edge regions of the integrated circuit die; disposing a molding material disposed around the integrated circuit die and the dam structure; and forming an interconnect structure over the integrated circuit die and the molding material.

22 . The method according to claim 21 , wherein the plurality of contact pads are formed having a first height, and wherein the dam structure is formed having a second height, the second height being greater than or about the same as the first height.

23 . The method according to claim 21 , further comprising removing a top portion of the molding material to have the second height proximate the dam structure.

24 . The method according to claim 21 , further comprising removing a top portion of the molding material and a top portion of the dam structure.

25 . The method according to claim 21 , wherein the dam structure comprises a material selected from the group consisting essentially of polyimide (PI), polybenzoxazole (PBO), underfill (UF) material, patternable epoxy, unremovable photoresist, solder mask material, and combinations thereof.

26 . The method according to claim 21 , further comprising filling in recesses in a top surface of the molding material.

27 . The method according to claim 26 , wherein the recesses are filled with a dielectric layer of the interconnect structure.

28 . The method according to claim 21 , wherein forming the interconnect structure includes forming a dielectric layer on a top surface of the molding material and forming a metal line in the dielectric layer.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Yu Chen-Hua
• Liu Chung-Shi
• Chen Meng-Tse
• Huang Hui-Min
• Huang Chih-Fan
• Cheng Ming-Da

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W70/09

  extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title