Semiconductor device and method of manufacturing the same

US2016013142A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016013142-A1
Application numberUS-201514792461-A
CountryUS
Kind codeA1
Filing dateJul 6, 2015
Priority dateJul 9, 2014
Publication dateJan 14, 2016
Grant date

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An improvement is achieved in the reliability of a semiconductor device. Over a semiconductor substrate, an interlayer insulating film is formed and, over the interlayer insulating film, a pad is formed. Over the interlayer insulating film, an insulating film is formed so as to cover the pad. In the insulating film, an opening is formed to expose a part of the pad. The pad is a pad to which a copper wire is to be electrically coupled and which includes an Al-containing conductive film containing aluminum as a main component. Over the Al-containing conductive film in a region overlapping the opening in plan view, a laminated film including a barrier conductor film, and a metal film over the barrier conductor film is formed. The metal film is in an uppermost layer. The barrier conductor film is a single-layer film or a laminated film including one or more layers of films selected from the group consisting of a Ti film, a TiN film, a Ta film, a TaN film, a W film, a WN film, a TiW film, and a TaW film. The metal film is made of one or more metals selected from the group consisting of Pd, Au, Ru, Rh, Pt, and Ir.

First claim

Opening claim text (preview).

What is claimed is: 1 . A semiconductor device, comprising: a semiconductor substrate; a first insulating film formed over the semiconductor substrate; a pad formed over the first insulating film; a second insulating film formed over the first insulating film so as to cover the pad; and an opening formed in the second insulating film to expose a part of the pad, wherein the pad is a pad to which a copper wire is to be electrically coupled and which includes an Al-containing conductive film containing aluminum as a main component, wherein, over the Al-containing conductive film in a region overlapping the opening in plan view, a first laminated film including a first conductor film, and a second conductor film over the first conductor film is formed, wherein the second conductor film is in an uppermost layer of the first laminated film, wherein the first conductor film is a single-layer film or a laminated film including one or more layers of films selected from the group consisting of a titanium film, a titanium nitride film, a tantalum film, a tantalum nitride film, a tungsten film, a tungsten nitride film, a titanium-tungsten film, and a tantalum-tungsten film, and wherein the second conductor film is made of one or more metals selected from the group consisting of palladium, gold, ruthenium, rhodium, platinum, and iridium. 2 . The semiconductor device according to claim 1 , wherein the second conductor film is a palladium film. 3 . The semiconductor device according to claim 2 , wherein the first conductor film includes a titanium film and, over the titanium film, the second conductor film is formed. 4 . The semiconductor device according to claim 2 , wherein the first conductor film is a titanium film. 5 . The semiconductor device according to claim 2 , wherein the second conductor film is formed by a sputtering method. 6 . The semiconductor device according to claim 1 , wherein, over a portion of the Al-containing conductive film which is covered with the second insulating film, the laminated film including the first conductor film, and the second conductor film over the first conductor film is not formed. 7 . The semiconductor device according to claim 1 , wherein the laminated film including the first conductor film, and the second conductor film over the first conductor film is formed over an entire upper surface of the Al-containing conductive film included in the pad. 8 . A semiconductor device, comprising: a semiconductor chip having a pad over a main surface thereof; a copper wire electrically coupled to the pad of the semiconductor chip; and a resin sealing portion sealing therein the semiconductor chip, and the copper wire, wherein the pad includes an Al-containing conductive film containing aluminum as a main component, wherein, between the copper wire and the Al-containing conductive film, a first laminated film including a first conductor film, and a second conductor film over the first conductor film is interposed, wherein the copper wire is bonded to the second conductor film, wherein the first conductor film is a single-layer film or a laminated film including one or more layers of films selected from the group consisting of a titanium film, a titanium nitride film, a tantalum film, a tantalum nitride film, a tungsten film, a tungsten nitride film, a titanium-tungsten film, and a tantalum-tungsten film, and wherein the second conductor film is made of one or more metals selected from the group consisting of palladium, gold, ruthenium, rhodium, platinum, and iridium. 9 . The semiconductor device according to claim 8 , wherein the second conductor film is a palladium film. 10 . The semiconductor device according to claim 9 , wherein the first conductor film includes a titanium film, and wherein, over the titanium film, the second conductor film is formed. 11 . The semiconductor device according to claim 9 , wherein the first conductor film is a titanium film. 12 . The semiconductor device according to claim 8 , wherein, at a junction interface between the copper wire and the second conductor film, a reaction layer between the copper wire and the second conductor film is formed. 13 . A method of manufacturing a semiconductor device, comprising the steps of: (a) providing a semiconductor substrate; (b) forming, over a main surface the semiconductor substrate, a first insulating film; (c) forming, over the first insulating film, an Al-containing conductive film containing aluminum as a main component; (d) patterning the Al-containing conductive film to form a pad; (e) forming, over the first insulating film, a second insulating film so as to cover the pad therewith; (f) forming an opening in the second insulating film; (g) electrically coupling a copper wire to the pad exposed from the opening; (h) after the step (c) and before the step (g), forming a first conductor film over the Al-containing conductive film; and (i) after the step (h) and before the step (g), forming a second conductor film over the first conductor film, wherein the first conductor film is a single-layer film or a laminated film including one or more layers of films selected from the group consisting of a titanium film, a titanium nitride film, a tantalum film, a tantalum nitride film, a tungsten film, a tungsten nitride film, a titanium-tungsten film, and a tantalum-tungsten film, wherein the second conductor film is made of one or more metals selected from the group consisting of palladium, gold, ruthenium, rhodium, platinum, and iridium, and wherein, in the step (g), the copper wire is bonded to the second conductor film. 14 . The method of manufacturing the semiconductor device according to claim 13 , wherein, in the step (i), the second conductor film is formed by a sputtering method. 15 . The method of manufacturing the semiconductor device according to claim 14 , wherein the second conductor film is a palladium film. 16 . The method of manufacturing the semiconductor device according to claim 15 , wherein the first conductor film is a titanium film. 17 . The method of manufacturing the semiconductor device according to claim 16 , wherein, in the step (h), the first conductor film is formed by a sputtering method. 18 . The method of manufacturing the semiconductor device according to claim 13 , wherein the steps (h) and (i) are performed after the step (f) and before the step (g). 19 . The method of manufacturing the semiconductor device according to claim 13 , wherein the step (h) is performed after the step (c) and before the step (d), wherein, in the step (d), a laminated film including the Al-containing conductive film, and the first conductor film over the Al-containing conductive film is patterned to form the pad, and wherein the step (i) is performed after the step (f) and before the step (g). 20 . The method of manufacturing a semiconductor device according to claim 13 , wherein the steps (h) and (i) are performed after the step (c) and before the step (d), and wherein, in the step (d), a laminated film including the Al-containing conductive film, the first conductor film over the Al-containing conductive film, and the second conductor film over the first conductor film is patterned to form the pad.

Assignees

Inventors

Classifications

  • between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • Encapsulations, e.g. protective coatings · CPC title

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What does patent US2016013142A1 cover?
An improvement is achieved in the reliability of a semiconductor device. Over a semiconductor substrate, an interlayer insulating film is formed and, over the interlayer insulating film, a pad is formed. Over the interlayer insulating film, an insulating film is formed so as to cover the pad. In the insulating film, an opening is formed to expose a part of the pad. The pad is a pad to which a c…
Who is the assignee on this patent?
Renesas Electronics Corp
What technology area does this patent fall under?
Primary CPC classification H10W72/019. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Jan 14 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).