Package structure and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-2016013123-A1
Application number	US-201414562972-A
Country	US
Kind code	A1
Filing date	Dec 8, 2014
Priority date	Jul 11, 2014
Publication date	Jan 14, 2016
Grant date	—

Abstract

A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a plurality of bonding pads; laminating a dielectric layer on the carrier; forming a plurality of conductive posts in the dielectric layer; and forming a cavity in the dielectric layer to expose the bonding pads, wherein the conductive posts are positioned around a periphery of the cavity, thereby simplifying the fabrication process.

First claim

What is claimed is:

1 . A package structure, comprising:
a carrier having a plurality of bonding pads; a dielectric layer having opposite first and second surfaces and formed on the carrier via the first surface thereof, wherein at least a cavity is formed in the second surface of the dielectric layer to expose the bonding pads; and a plurality of conductive posts formed in the dielectric layer and positioned around a periphery of the cavity.

2 . The structure of claim 1 , wherein the carrier is a packaging substrate, a semiconductor chip, a wafer, an interposer, or a packaged or unpackaged semiconductor element.

3 . The structure of claim 1 , wherein a circuit layer is formed on the second surface of the dielectric layer and electrically connected to the conductive posts.

4 . The structure of claim 1 , wherein the dielectric layer is made of a photo imageable dielectric material.

5 . The structure of claim 1 , further comprising an electronic element disposed in the cavity and electrically connected the bonding pads.

6 . A method for fabricating a package structure, comprising the steps of:
providing a carrier having a plurality of bonding pads and a dielectric layer having opposite first and second surfaces; laminating the dielectric layer on the carrier via the first surface thereof, wherein the bonding pads are covered by the dielectric layer; forming a plurality of conductive posts in the dielectric layer; and forming at least a cavity in the second surface of the dielectric layer so as to expose the bonding pads, wherein the conductive posts are positioned around a periphery of the cavity.

7 . The method of claim 6 , wherein the carrier is a packaging substrate, a semiconductor chip, a wafer, an interposer, or a packaged or unpackaged semiconductor element.

8 . The method of claim 6 , wherein the second surface of the dielectric layer has a conductive layer used for forming the conductive posts.

9 . The method of claim 6 , wherein forming the conductive posts comprises:
forming a plurality of through holes penetrating the dielectric layer; and filling a conductive material in the through holes to form the conductive posts.

10 . The method of claim 6 , wherein the second surface of the dielectric layer has a circuit layer electrically connected to the conductive posts.

11 . The method of claim 6 , wherein the dielectric layer is made of a photo imageable dielectric material.

12 . The method of claim 11 , wherein the cavity is formed by exposure and development.

13 . The method of claim 6 , further comprising disposing an electronic element in the cavity, wherein the electronic element is electrically connected to the bonding pads.

14 . The method of claim 6 , further comprising stacking a stack member on the second surface of the dielectric layer, wherein the stack member is electrically connected to the conductive posts.

15 . The method of claim 14 , wherein the stack member is a packaging substrate, a semiconductor chip, an interposer or a package.

Assignees

• Siliconware Precision Industries Co Ltd

Inventors

• Pai Yu-Cheng
• Lin Chun-Hsien
• Chiu Shih-Chao
• Hsiao Wei-Chung
• Sun Ming-Chen
• Shen Tzu-Chieh
• Chen Chia-Cheng

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W70/682

  comprising holes having chips therein · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title