Semiconductor memory device including three-dimensional array structure

Patent metadata

Field	Value
Publication number	US-2016012893-A1
Application number	US-201414570535-A
Country	US
Kind code	A1
Filing date	Dec 15, 2014
Priority date	Jul 10, 2014
Publication date	Jan 14, 2016
Grant date	—

Abstract

A semiconductor memory device may include source selection transistors coupled to a common source line, source side dummy memory cells coupled between the source selection transistors and the normal memory cells, and drain selection transistors coupled to a bit line. The semiconductor memory device may include drain side dummy memory cells coupled between the drain selection transistors and the normal memory cells. A number of the source side dummy memory cells is less than a number of the drain side dummy memory cells, and a number of the drain selection transistors may be greater than the source selection transistors.

First claim

What is claimed is:

1 . A semiconductor memory device including normal memory cells stacked over a substrate, the semiconductor memory device comprising:
source selection transistors coupled to a common source line; source side dummy memory cells coupled between the source selection transistors and the normal memory cells; drain selection transistors coupled to a bit line; and drain side dummy memory cells coupled between the drain selection transistors and the normal memory cells, wherein a number of the source side dummy memory cells is less than a number of the drain side dummy memory cells, and wherein a number of the drain selection transistors is greater than a number of the source selection transistors.

2 . The semiconductor memory device of claim 1 , wherein the number of the drain selection transistors is greater than the number of the source selection transistors by a difference between the number of the drain side dummy memory cells and the number of the source side dummy memory cells.

3 . The semiconductor memory device of claim 1 , wherein the drain selection transistors include first drain selection transistors and second drain selection transistors coupled in series with each other,
the first drain selection transistors are coupled in common to a first drain selection line, and the second drain selection transistors are coupled in common to a second drain selection line.

4 . The semiconductor memory device of claim 1 , wherein the source selection transistors are coupled in common to a single source selection line.

5 . The semiconductor memory device of claim 1 , further comprising a pipe transistor,
wherein the source selection transistors, the source side dummy memory cells and first normal memory cells, among the normal memory cells, form a first sub-cell string, second normal memory cells, among the normal memory cells, the drain side dummy memory cells and the drain selection transistors form a second sub-cell string, and the first and second sub-cell strings are coupled through the pipe transistor.

6 . The semiconductor memory device of claim 5 , wherein a height of the first sub-cell string from the pipe transistor is substantially equal to a height of the second sub-cell string from the pipe transistor.

7 . The semiconductor memory device of claim 6 , wherein a number of the first normal memory cells is greater than a number of the second normal memory cells.

8 . The semiconductor memory device of claim 5 , wherein the first normal memory cells, the source side dummy memory cells and the source selection transistors are sequentially stacked in a direction crossing the substrate, and
the second normal memory cells, the drain side dummy memory cells and the drain selection transistors are sequentially stacked in the direction crossing the substrate.

9 . The semiconductor memory device of claim 1 , wherein the source selection transistors, the source side dummy memory cells, the normal memory cells, the drain side dummy memory cells and the drain selection transistors are sequentially stacked in a direction crossing the substrate.

10 . A semiconductor memory device, comprising:
a pipe transistor; a first sub-cell string extending between the pipe transistor and a common source line and including source selection transistors coupled to the common source line and source side dummy memory cells coupled to the source selection transistors; and a second sub-cell string extending between the pipe transistor and a bit line and including drain selection transistors coupled to the bit line and drain side dummy memory cells coupled to the drain selection transistors, wherein a number of the source side dummy memory cells is less than a number of the drain side dummy memory cells, and a number of the drain selection transistors is greater than a number of the source selection transistors.

11 . The semiconductor memory device of claim 10 , wherein the number of the drain selection transistors is greater than the number of the source selection transistors by a difference between the number of the drain side dummy memory cells and the number of the source side dummy memory cells.

12 . The semiconductor memory device of claim 10 , wherein a height of the first sub-cell string from the pipe transistor is substantially equal to a height of the second sub-cell string from the pipe transistor.

13 . The semiconductor memory device of claim 10 , wherein the first sub-cell string includes first normal memory cells coupled in series between the source side dummy memory cells and the pipe transistor, and
the second sub-cell string includes second normal memory cells coupled in series between the drain side dummy memory cells and the pipe transistor.

14 . The semiconductor memory device of claim 13 , wherein a number of the first normal memory cells is greater than a number of the second normal memory cells.

15 . The semiconductor memory device of claim 14 , wherein the number of the first normal memory cells is greater than the number of the second normal memory cells by a sum of a difference between the number of the source side dummy memory cells and the number of the drain side dummy memory cells and a difference between the number of the source selection transistors and the number of the drain selection transistors.

16 . The semiconductor memory device of claim 10 , wherein the drain selection transistors include first drain selection transistors and second drain selection transistors coupled in series with each other,
the first drain selection transistors are coupled in common to a first drain selection line, and the second drain selection transistors are coupled in common to a second drain selection line.

17 . The semiconductor memory device of claim 10 , wherein the source selection transistors are coupled in common to a single source selection line.

18 . A semiconductor memory device including:
a first sub-cell string stacked over a substrate and including a first set of normal memory cells; a second sub-cell string stacked over the substrate and including a second set of normal memory cells; drain selection transistors coupled to the second set of normal memory cells; and source selection transistors coupled to the first set of normal memory cells, wherein the first and second sub-cell strings are configured to reduce leakage current of the normal memory cells by including greater numbers of the drain selection transistors in the second sub-cell string than the source selection transistors in the first sub-cell string.

19 . The semiconductor memory device of claim 18 , wherein a height of the first sub-cell string from the substrate is substantially equal to a height of the second sub-cell string from the substrate.

20 . The semiconductor memory device of claim 18 , further comprising:
source side dummy memory cells coupled between the source selection transistors and the first set of normal memory cells; and drain side dummy memory cells coupled between the drain selection transistors and the second set of normal memory cells, wherein a number of the source side dummy memory cells is less than a number of the drain side dummy memory cells.

Assignees

• Sk Hynix Inc

Inventors

• Ahn Jung Ryul
• Lee Yun Kyoung

Classifications

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• H10B41/35 Primary

  with a cell select transistor, e.g. NAND · CPC title

• H10B41/30

  characterised by the memory core region · CPC title

• G11C29/82

  for EEPROMs · CPC title

• H10B43/40

  characterised by the peripheral circuit region · CPC title