Multistage amplifier circuit with improved settling time

US2016006403A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016006403-A1
Application numberUS-201514790592-A
CountryUS
Kind codeA1
Filing dateJul 2, 2015
Priority dateJul 2, 2014
Publication dateJan 7, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Described examples include multistage amplifier circuits having first and second forward circuits, a comparator or sensor circuit coupled to sense a signal in the second forward circuit to identify nonlinear operation or slewing conditions in the multistage amplifier circuit, and one or more sample hold circuits operative according to a sensor circuit output signal to selectively maintain the amplitude of an amplifier input signal in the second forward circuit and/or in a feedback circuit in response to the sensor circuit output signal indicating nonlinear operation or slewing conditions in the multistage amplifier circuit. Certain examples further include a clamping circuit operative to selectively maintain a voltage at a terminal of a Miller compensation capacitance responsive to the comparator output signal indicating nonlinear operation or slewing conditions.

First claim

Opening claim text (preview).

The following is claimed: 1 . A multistage amplifier circuit, comprising: a first forward circuit, including a first amplifier having a first amplifier input to receive an input signal, and a second amplifier having a second amplifier input coupled with an output of the first amplifier, the second amplifier including a second amplifier output providing an output signal; a second forward circuit, including a third amplifier having a third amplifier input coupled to receive the input signal, a fourth amplifier having a fourth amplifier input coupled with an output of the third amplifier, and a fifth amplifier having a fifth amplifier input coupled with an output of the fourth amplifier, the fifth amplifier having a fifth amplifier output coupled with the second amplifier input; a sensor circuit coupled with the second forward circuit to sense nonlinear operation or slewing conditions of the multistage amplifier circuit, the comparator having a sensor circuit output providing a sensor circuit output signal in a first state when nonlinear operation or slewing conditions are sensed in the multistage amplifier circuit, and a second state when no nonlinear operation or slewing conditions are sensed in the multistage amplifier circuit; and a first sample hold circuit coupled with the fifth amplifier input to maintain an amplitude of a signal at the fifth amplifier input when the sensor circuit output signal is in the first state. 2 . The multistage amplifier circuit of claim 1 , wherein the sensor circuit is a comparator circuit including a first comparator input coupled with a first differential input of the fourth amplifier, a second comparator input coupled with a second differential input of the fourth amplifier, and comparator output providing the sensor circuit output signal. 3 . The multistage amplifier circuit of claim 2 , wherein the input signal is a differential signal, and wherein the second forward circuit comprises: a first chopper circuit coupled between the first amplifier input and the third amplifier, the first chopper circuit including a first switching circuit to alternately invert the input signal according to a clock signal to provide a first chopped differential input signal to the third amplifier input; and a second chopper circuit coupled between the third amplifier and the fourth amplifier, the second chopper circuit including a second switching circuit to alternately invert a differential output signal from the output of the third amplifier according to the clock signal to provide a second chopped differential input signal to the fourth amplifier input. 4 . The multistage amplifier circuit of claim 2 , comprising: a compensation capacitance including a first terminal coupled with the second amplifier output, and a second terminal coupled with the fourth amplifier input; and a clamp circuit coupled with the fourth amplifier input to selectively maintain a voltage at the second terminal of the compensation capacitance when the sensor circuit output signal is in the first state. 5 . The multistage amplifier circuit of claim 4 , wherein the clamp circuit is operative to drive a voltage at the first differential input of the fourth amplifier to a voltage at the second differential input of the fourth amplifier when the sensor circuit output signal is in the first state. 6 . The multistage amplifier circuit of claim 5 , comprising: a third circuit providing a feedback loop to the second forward circuit, the third circuit including: a sixth amplifier having a sixth amplifier input coupled with the fourth amplifier input, a seventh amplifier having a seventh amplifier input coupled with an output of the sixth amplifier, and a notch filter coupled between the output of the sixth amplifier and the seventh amplifier input; and a second sample hold circuit coupled with the seventh amplifier input to maintain an amplitude of a signal at the seventh amplifier input when the sensor circuit output signal is in the first state. 7 . The multistage amplifier circuit of claim 6 , wherein the input signal is a differential signal, and wherein the second forward circuit comprises: a first chopper circuit coupled between the first amplifier input and the third amplifier, the first chopper circuit including a first switching circuit to alternately invert the input signal according to a clock signal to provide a first chopped differential input signal to the third amplifier input; and a second chopper circuit coupled between the third amplifier and the fourth amplifier, the second chopper circuit including a second switching circuit to alternately invert a differential output signal from the output of the third amplifier according to the clock signal to provide a second chopped differential input signal to the fourth amplifier input. 8 . The multistage amplifier circuit of claim 7 , wherein the third circuit includes a third chopper circuit coupled between the output of the sixth amplifier and the notch filter, the third chopper circuit including a third switching circuit to alternately invert a differential output signal of the sixth amplifier according to the clock signal to provide a third chopped differential input signal to the notch filter. 9 . The multistage amplifier circuit of claim 1 , comprising: a compensation capacitance including a first terminal coupled with the second amplifier output, and a second terminal coupled with the fourth amplifier input; and a clamp circuit coupled with the fourth amplifier input to selectively maintain a voltage at the second terminal of the compensation capacitance when the sensor circuit output signal is in the first state. 10 . The multistage amplifier circuit of claim 9 , wherein the clamp circuit is operative to drive a voltage at the first differential input of the fourth amplifier to a voltage at the second differential input of the fourth amplifier when the sensor circuit output signal is in the first state. 11 . The multistage amplifier circuit of claim 1 , comprising: a third circuit providing a feedback loop to the second forward circuit, the third circuit including: a sixth amplifier having a sixth amplifier input coupled with the fourth amplifier input, a seventh amplifier having a seventh amplifier input coupled with an output of the sixth amplifier, and a notch filter coupled between the output of the sixth amplifier and the seventh amplifier input; and a second sample hold circuit coupled with the seventh amplifier input to maintain an amplitude of a signal at the seventh amplifier input when the sensor circuit output signal is in the first state. 12 . The multistage amplifier circuit of claim 1 , comprising: a third circuit providing a feedback loop to the second forward circuit, the third circuit including: a sixth amplifier having a sixth amplifier input coupled with the fourth amplifier input, and a seventh amplifier having a seventh amplifier input coupled with an output of the sixth amplifier; and a second sample hold circuit coupled with the seventh amplifier input to maintain an amplitude of a signal at the seventh amplifier input when the sensor circuit output signal is in the first state. 13 . The multistage amplifier circuit of claim 12 , wherein the third circuit includes a notch filter coupled between the output of the sixth amplifier and the seventh amplifier input. 14 . The multistage amplifier circuit of claim 12 , wherein the first, third, fourth, fifth, sixth and seventh amplifiers are transconductance amplifiers with differential inputs and differential outputs. 15 . The multistage am

Assignees

Inventors

Classifications

  • Mirror types · CPC title

  • in differential amplifiers · CPC title

  • by use of neutralising means · CPC title

  • with FET's · CPC title

  • there being a feedback over one or more internal stages in the global amplifier · CPC title

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What does patent US2016006403A1 cover?
Described examples include multistage amplifier circuits having first and second forward circuits, a comparator or sensor circuit coupled to sense a signal in the second forward circuit to identify nonlinear operation or slewing conditions in the multistage amplifier circuit, and one or more sample hold circuits operative according to a sensor circuit output signal to selectively maintain the a…
Who is the assignee on this patent?
Texas Instruments Inc
What technology area does this patent fall under?
Primary CPC classification H03F1/3223. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Jan 07 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).