Structure and method for single gate non-volatile memory device

Patent metadata

Field	Value
Publication number	US-2016005751-A1
Application number	US-201514854336-A
Country	US
Kind code	A1
Filing date	Sep 15, 2015
Priority date	Jul 18, 2011
Publication date	Jan 7, 2016
Grant date	—

Abstract

The present disclosure provides an integrated circuit. The integrated circuit includes a substrate; a field effect transistor disposed in a periphery region of the substrate, the field effect transistor including a gate electrode, a first source, a first drain; a floating gate non-volatile memory device disposed in a memory region of the substrate, the floating gate non-volatile memory device including a second source, a third source, and a second drain, wherein the second source, the third source, and the second drain are disposed along an axis; and a floating gate electrode in the memory region including a first portion, a second portion, and a third portion, wherein the first portion, the second portion, and the third portion are electrically connected, wherein the first portion, the second portion and the third portion extend perpendicular to the axis.

First claim

What is claimed is:

1 . An integrated circuit, comprising:
a semiconductor substrate having a periphery region and a memory region; a field effect transistor disposed in the periphery region, the field effect transistor including a gate electrode, a first source and a first drain; a floating gate non-volatile memory device disposed in the memory region, the floating gate non-volatile memory device including a second source, a third source, and a second drain,
wherein the second source, the third source, and the second drain are arranged along an axis,
wherein the second drain is disposed between the second source and the third source; and
a floating gate electrode in the memory region including a first portion, a second portion, and a third portion,
wherein the first portion, the second portion, and the third portion are electrically coupled,
wherein the first portion, the second portion and the third portion extend perpendicular to the axis,
wherein the first portion is disposed on a first channel, the first channel extending between the second source and the second drain,
wherein the second portion includes a first side surface and a second side surface opposite the first side surface,
wherein each of the first side surface and the second side surface is disposed directly above the second drain, and
wherein the third portion is disposed on a second channel, the second channel extending between the third source and the second drain.

2 . The integrated circuit of claim 1 further comprising:
a first trench isolation feature disposed in the periphery region;
a second trench isolation feature disposed in the periphery region, wherein the field effect transistor is disposed between the first trench isolation feature and the second trench isolation feature.

3 . The integrated circuit of claim 1 wherein the first source is disposed between the gate electrode and the first trench isolation feature,
wherein the first drain is disposed between the gate electrode and the second trench isolation feature.

4 . The integrated circuit of claim 1 wherein the semiconductor substrate includes a first type of dopant in the periphery region,
wherein the first source and the first drain include a second type of dopant.

5 . The integrated circuit of claim 1 wherein the gate electrode is in contact with a first gate dielectric, the first gate dielectric being in contact with a channel between the first source and the first drain.

6 . The integrated circuit of claim 1 wherein the first portion is in contact with a second gate dielectric, the second gate dielectric being in contact with the first channel,
wherein the third portion is in contact with a third gate dielectric, the third gate dielectric being in contact with the second channel,
wherein the semiconductor substrate includes a first type of dopant in the memory region,
wherein the first channel and the second channel include the first type of dopant.

7 . The integrated circuit of claim 1 wherein the first portion, the second portion, and the third portion each have a rectangular shape.

8 . The integrated circuit of claim 1 wherein the first portion, the second portion, and the third portion are physically connected by a fourth portion of the floating gate electrode, the fourth portion extending parallel to the axis.

9 . The integrated circuit of claim 1 further comprising:
an active region, the active region including a first region extending along the axis and a second region extending from the first region in a direction perpendicular to the axis;
the second source being formed in a first end portion of the first region;
the third source being formed in a second end portion of the first region; and
the second drain being formed in at the intersection of the first region and the second region.

10 . The integrated circuit of claim 1 further comprising:
a first contact feature disposed on the second drain.
a second contact feature disposed on the second source.
a third contact feature disposed on the third source.

11 . The integrated circuit of claim 1 wherein the semiconductor substrate includes a first type of dopant in the memory region,
wherein the second source, the third source and the second drain include a second type of dopant that is different from the first type of dopant.

12 . An integrated circuit, comprising:
a semiconductor substrate having a periphery region and a memory region; a field effect transistor disposed in the periphery region; and a floating gate non-volatile memory device disposed in the memory region,
wherein the floating gate non-volatile memory device includes an active region having a first elongated region extended along a first axis and a second elongated region connected with the first elongated region and extended along a second axis perpendicular to the first axis,
wherein the floating gate non-volatile memory device includes a floating gate having a first elongated portion that is extended along the first axis, a second elongated portion that is extended along the second axis, a third elongated portion that is extended along the second axis, and a fourth elongated portion that is extended along the second axis,
wherein the second, third and fourth elongated portions contact the first elongated portion,
wherein the floating gate non-volatile memory device includes a first source formed in a first end portion of the first elongated region,
wherein the floating gate non-volatile memory device includes a second source formed in a second end portion of the first elongated region, and
wherein the floating gate non-volatile memory device in the memory region includes a drain formed in a central portion of the first elongated region, the drain extending throughout the second elongated region, wherein the drain spans from the second elongated portion to the fourth elongated portion along the first axis.

13 . The integrated circuit of claim 12 wherein the second elongated portion is disposed on the drain.

14 . The integrated circuit of claim 12 wherein the first elongated region is spaced away from the active region.

15 . The integrated circuit of claim 12 , further comprising:
a contact feature disposed on the drain in the second elongated region.

16 . An integrated circuit, comprising:
a substrate; a field effect transistor disposed in a periphery region of the substrate, the field effect transistor including a gate electrode, a first source, a first drain; a floating gate non-volatile memory device disposed in a memory region of the substrate, the floating gate non-volatile memory device including a second source, a third source, and a second drain, wherein the second source, the third source, and the second drain are disposed along an axis; and a floating gate electrode in the memory region including a first portion, a second portion, and a third portion, wherein the first portion, the second portion, and the third portion are electrically connected, wherein the first portion, the second portion and the third portion extend perpendicular to the axis.

17 . The integrated circuit of claim 16 wherein the substrate includes a first type of dopant,
wherein the second source, the third source and the second drain include a second type of dopant that is different from the first type of dopant, wherein the second drain is disposed between the second source and the third source.

18 . The integrated circuit of claim 16 wherein the first portion is overlying a first channel, the first

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Tsui Felix Ying-Kit
• Tseng Huang-Wen

Classifications

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10B69/00

  Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices · CPC title

• H10D30/681 Primary

  having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688) · CPC title

• H10D84/017

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title