Chip packaging method, chip packaging module, and embedded substrate chip packaging structure
US-2024413138-A1 · Dec 12, 2024 · US
US2016005672A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016005672-A1 |
| Application number | US-201414323077-A |
| Country | US |
| Kind code | A1 |
| Filing date | Jul 3, 2014 |
| Priority date | Jul 3, 2014 |
| Publication date | Jan 7, 2016 |
| Grant date | — |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
Some embodiments relate to an electronic package. The electronic package includes a substrate and a die attached to the substrate. The electronic package further includes an underfill positioned between the die and the substrate due to capillary action. A support surrounds the die. The support provides the same beneficial fillet geometry on all die edges. Therefore, the support provides similar stress reduction on all die edges. Other embodiments relate to method of fabricating an electronic package. The method includes attaching a die to a substrate and inserting an underfill between the die and the substrate using capillary action. The method further includes placing a support around the die such that the support surrounds the die.
Opening claim text (preview).
1 . An electronic package comprising: a substrate; a die attached to the substrate; an underfill positioned between the die and the substrate due to capillary action; and a support surrounding the die. 2 . The electronic package of claim 1 , wherein the die is flip chip bonded to the substrate. 3 . The electronic package of claim 1 , wherein the underfill secures the support to the substrate. 4 . The electronic package of claim 1 , wherein the underfill secures the support to the die. 5 . The electronic package of claim 1 , wherein the support has a substantially uniform cross-section. 6 . The electronic package of claim 1 , wherein the support has an inner bottom edge and an outer bottom edge, the inner bottom edge being chamfered to receive underfill when the support is mounted around the die. 7 . The electronic package of claim 6 , wherein the support has an inner upper edge and an inner outer upper edge, the inner upper edge including a channel to receive excess underfill that flows upward between the die and the support when the support is mounted around the die. 8 . The electronic package of claim 1 , wherein the cross-section of the support changes such that the cross-section is larger in areas of relatively higher stress on the die and smaller in areas of relatively lower stress on the die. 9 . The electronic package of claim 1 , wherein the support has an inner lower edge and an outer lower edge, the support including a passage and an outer surface, the passage extending from the inner lower edge of the support to the outer surface of the support such that the underfill flows from the outer surface through the passage to the inner lower edge when the support is mounted around the die. 10 . The electronic package of claim 9 , wherein the passage extends from the outer surface of the support on one side of the support. 11 . A method comprising: attaching a die to a substrate; inserting an underfill between the die and the substrate using capillary action; and placing a support around the die such that the support surrounds the die. 12 . The method of claim 11 , wherein attaching the die to the substrate includes attaching the die to the substrate using flip chip bonding. 13 . The method of claim 11 , wherein placing a support around the die such that the support surrounds the die includes attaching the support to the die using the underfill. 14 . The method of claim 11 , wherein placing a support around the die such that the support surrounds the die includes attaching the support to the substrate using the underfill. 15 . The method of claim 11 , further comprising curing the underfill. 16 . The method of claim 11 , further comprising removing underfill through open areas in the support. 17 . The method of claim 11 , wherein inserting an underfill between the die and the substrate using capillary action includes inserting the underfill through a passage in the support from an outer surface of the support to a lower inner edge of the support. 18 . An electronic package comprising: a die; a support molded to the die, wherein the support surrounds the die; a substrate; and an underfill that attaches the die and the support to the substrate due to capillary action of the underfill between the support and the die and the substrate. 19 . The electronic package of claim 18 , wherein the die is flip chip bonded to the substrate. 20 . The electronic package of claim 18 , wherein the substrate includes a plurality of redistribution layers and the underfill attaches the die and the support to at least one of the redistribution layers that form the substrate. 21 . The electronic package of claim 18 , wherein the support has a substantially uniform cross-section. 22 . A method comprising: molding a die to a support such that the support surrounds the die; placing the die and the support adjacent to a substrate; and inserting an underfill between the substrate and the die and support using capillary action. 23 . The method of claim 22 , wherein placing the die and the support adjacent to the substrate includes attaching the die to the substrate using flip chip bonding. 24 . The method of claim 22 , further comprising curing the underfill. 25 . The method of claim 22 , further comprising separating the die and the support from a wafer that includes a plurality of dies and a plurality of supports.
between a chip and a stacked insulating package substrate, interposer or RDL · CPC title
between a chip and a stacked insulating package substrate, interposer or RDL · CPC title
Connecting techniques · CPC title
Bump connectors and die-attach connectors (bumps embedded in underfills H10W74/15) · CPC title
Solid or gel fillings · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.