Integrated circuit fabrication

Patent metadata

Field	Value
Publication number	US-2016005601-A1
Application number	US-201514855845-A
Country	US
Kind code	A1
Filing date	Sep 16, 2015
Priority date	Mar 28, 2005
Publication date	Jan 7, 2016
Grant date	—

Abstract

A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

First claim

1 . (canceled)

2 . A method for integrated circuit fabrication, comprising:
forming a plurality of loops of masking material over a substrate; depositing a selectively definable material over the loops; and patterning the selectively definable material to expose expanses of the loops between ends of the loops, wherein the ends remain covered by the selectively definable material after patterning, wherein an entire width of a portion of the masking material at the ends is covered by the selectively definable material, wherein patterning defines features in the selectively definable material, the features spaced apart from the loops and having a minimum width larger than a minimum width of the masking material forming the loops.

3 . The method of claim 2 , wherein forming the plurality of loops forms pairs of parallel runs of the masking material, each pair of parallel runs joining at the ends of the loops.

4 . The method of claim 3 , wherein, after patterning, the selectively definable material extends completely over the ends of at least some of the loops, the selectively definable material extending completely from a portion of one run of the masking material to a portion of another, parallel run of the masking material.

5 . The method of claim 4 , wherein loops of the plurality of loops extend substantially parallel to one another,
wherein, after patterning, the selectively definable material extends continuously across the ends of all of the loops.

6 . The method of claim 2 , wherein forming the plurality of loops comprises:
forming a plurality of mandrels over the substrate; forming spacers at sides of the mandrels, the spacers looping around the mandrels; and selectively removing the mandrels relative to the spacers.

7 . The method of claim 6 , wherein providing the plurality of spacers comprises:
blanket depositing a spacer material on the mandrels; and directionally etching the deposited spacer material to define the spacers at the sides of the mandrels.

8 . The method of claim 2 , further comprising:
depositing planarizing material on and between the loops before depositing the selectively definable material.

9 . The method of claim 2 , wherein depositing the selectively definable material comprises depositing photoresist.

10 . A method for integrated circuit fabrication, comprising:
patterning a selectively definable material disposed over a plurality of loops of material over a substrate, wherein, after patterning:
ends of the loops remain completely covered by the selectively definable material;
expanses of the loops between the ends are exposed; and
features formed of the selectively definable material are disposed spaced apart from the exposed expanses of the loops; and
transferring a pattern defined by the loops and the selectively definable material to the substrate.

11 . The method of claim 10 , wherein transferring the pattern defines interconnects in an array region.

12 . The method of claim 11 , wherein the features formed of the selectively definable material are disposed in a periphery region.

13 . The method of claim 11 , wherein the array region is a memory cell array region.

14 . The method of claim 11 , wherein transferring the pattern forms openings in a dielectric material, further comprising:
depositing conductive material in the openings, the conductive material forming the interconnects.

15 . The method of claim 10 , wherein transferring the pattern exposes conductive plugs in the substrate.

16 . A method for integrated circuit fabrication, comprising:
forming a plurality of loops of material over a substrate, the material having a width as seem in a top down view; depositing a selectively definable material over the loops; patterning the selectively definable material, wherein, after patterning:
an entire width of a portion of the material forming the loops remains covered by the selectively definable material;
an expanse of the material is exposed away from the covered portion.

17 . The method of claim 16 , wherein the loops have an L-shape as seen in a top-down view.

18 . The method of claim 16 , further comprising:
subsequently etching the substrate through the patterned selectively definable material and the exposed expanse of material.

19 . The method of claim 18 , further comprising:
forming a masking layer above the substrate and underlying the plurality of loops; and etching the masking layer through the patterned selectively definable material and the exposed expanse of material.

20 . The method of claim 16 , wherein the loops comprise an oxide material.

21 . The method of claim 16 , wherein forming the plurality of loops of material comprises performing an atomic layer deposition.

Assignees

• Micron Technology Inc

Inventors

• Tran Luan C
• Lee John
• Liu Zengtao
• Freeman Eric
• Nielsen Russell

Classifications

• H10P76/4088 Primary

  Processes for improving the resolution of the masks · CPC title

• H10P76/4085 Primary

  characterised by the processes involved to create the masks · CPC title

• H10P50/693

  characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P50/73

  using masks for insulating materials · CPC title