Method and apparatus for fabricating semiconductor device

Patent metadata

Field	Value
Publication number	US-2016005590-A1
Application number	US-201514625907-A
Country	US
Kind code	A1
Filing date	Feb 19, 2015
Priority date	Jul 4, 2014
Publication date	Jan 7, 2016
Grant date	—

Abstract

A method for fabricating a semiconductor device includes obtaining first raw data by measuring an overlay of a semiconductor wafer of a first lot and generating a regression equation based on the first raw data. A semiconductor wafer of a second lot is aligned based on a coefficient of the regression equation, second raw data is obtained by measuring an overlay of the aligned semiconductor wafer of the second lot, and the regression equation is corrected based on the second raw data. Correction of the regression equation includes dividing the regression equation into an initial equation and a residual equation excluding the initial equation from the regression equation, correcting a coefficient of the initial equation; and correcting a coefficient of the residual equation.

First claim

What is claimed is:

1 . A method of fabricating a semiconductor device, the method comprising:
obtaining first raw data by measuring an overlay of a semiconductor wafer of a first lot; generating a regression equation based on the first raw data; aligning a semiconductor wafer of a second lot based on a coefficient of the regression equation; obtaining second raw data by measuring an overlay of the aligned semiconductor wafer of the second lot; and correcting the regression equation based on the second raw data, wherein the correcting of the regression equation includes: dividing the regression equation into an initial equation and a residual equation excluding the initial equation from the regression equation; correcting a coefficient of the initial equation by performing a first regression analysis of the initial equation based on the second raw data; and correcting a coefficient of the residual equation by applying the coefficient of the initial equation to the regression equation and performing a second regression analysis of the regression equation having the coefficient of the initial equation.

2 . The method as claimed in claim 1 , wherein an order of the initial equation is smaller than or equal to that of the regression equation.

3 . The method as claimed in claim 1 , wherein the first raw data includes:
a coordinate of the semiconductor wafer of the first lot in a first direction and a coordinate of the semiconductor wafer of the first lot in a second direction intersecting the first direction.

4 . The method as claimed in claim 3 , wherein variables of the regression equation include one or more of a coordinate in the first direction, a coordinate in a second direction, powers of the coordinates in the first direction and the second direction, and a product of the coordinate in the first direction and the coordinate in the second direction.

5 . The method as claimed in claim 1 , further comprising:
aligning a semiconductor wafer of a third lot based on the coefficient of the corrected regression equation.

6 . The method as claimed in claim 1 , wherein the regression equation has a third or higher order.

7 . The method as claimed in claim 1 , wherein performing the second regression analysis includes:
dividing the residual equation into a first residual equation of an order smaller than or equal to that of the residual equation and a second residual equation excluding the first residual equation from the residual equation; correcting a coefficient of the first residual equation by performing a third regression analysis of the first residual equation based on the second raw data; and correcting a coefficient of the second residual equation by performing a fourth regression analysis of the second residual equation based on the second raw data.

8 . The method as claimed in claim 1 , wherein the order of the initial equation is greater than or equal to that of the residual equation.

9 . The method as claimed in claim 1 , wherein dividing the regression equation includes determining whether to divide the regression equation by measuring variation inflation factor (VIF) values of the variables of the regression equation.

10 . The method as claimed in claim 9 , wherein determining whether to divide the regression equation includes:
performing a regression analysis of the regression equation as a whole without dividing the regression equation if a maximum value among the VIF values is less than a preset first value, dividing the regression equation into the initial equation and the residual equation if the maximum value among the VIF values is equal to or greater than the first value, and performing the first regression analysis and the second regression analysis.

11 . The method as claimed in claim 10 , wherein determining whether to divide the regression equation includes:
performing a regression analysis of the regression equation as a whole without dividing the regression equation if the maximum value among the VIF values is less than the preset first value, dividing the regression equation into the initial equation and the residual equation if the maximum value among the VIF values is equal to or greater than the first value or if an average value of the VIF values is equal to or greater than a preset second value, and performing the first regression analysis and the second regression analysis.

12 . The method as claimed in claim 1 , wherein:
the regression equation includes a first regression equation and a second regression equation, and aligning the semiconductor wafer of the second lot includes: aligning a coordinate of the semiconductor wafer of the second lot in the first direction using the first regression equation, and aligning a coordinate of the semiconductor wafer of the second lot in the second direction, which intersects the first direction, using the second regression equation.

13 . The method as claimed in claim 1 , wherein the order of the initial equation is equal to a lowest order among orders of terms of the regression equation.

14 . A method for performing a step-by-step (SBS) regression analysis used by a coefficient provider, the method comprising:
providing a regression equation based on the following equation:

Z
x

=

∑

i
=
0

n



∑

j
=
0

m



k
ij



x
i



y
j

where i, j, n, and m are integers of 0 or more, k ij is a real number, 0≦i, and j≦1;
determining a coefficient of an initial equation by performing a first regression analysis of the initial equation, which includes a constant and a first-order term of the regression equation, using raw data;
determining a coefficient of a residual equation excluding the initial equation from the regression equation by performing a second regression analysis of the residual equation using the raw data;
correcting the regression equation using the determined coefficients; and
outputting information including the corrected regression equation to align a semiconductor wafer and a reticle for a light exposure operation.

15 . The method as claimed in claim 14 , wherein:
x is a coordinate of a semiconductor wafer of a first lot in a first direction, and y is a coordinate of the semiconductor wafer of the first lot in a second direction intersecting the first direction.

16 . An apparatus for fabricating a semiconductor device, comprising:
an input to receive first raw data based on an overlay measurement of a semiconductor wafer of a first lot; a processor to perform operations including: a) generating a regression equation based on the first raw data; b

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Han-Hum
• Choi Sung-Won
• Han Chang-Ho

Classifications

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• G03F7/70633 Primary

  Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching · CPC title

• H01L21/02 Primary

  Electricity · mapped topic

• G05B2219/45031

  Manufacturing semiconductor wafers · CPC title