Data input circuit of semiconductor apparatus

Patent metadata

Field	Value
Publication number	US-2016004649-A1
Application number	US-201414513480-A
Country	US
Kind code	A1
Filing date	Oct 14, 2014
Priority date	Jul 7, 2014
Publication date	Jan 7, 2016
Grant date	—

Abstract

A data input circuit of a semiconductor apparatus may include a plurality of parallelizing units corresponding to a plurality of input/output pads in a one-to-one manner, and a data control block configured to transmit serial test data, which may be input through less than all of the plurality of input/output pads, to the plurality of parallelizing units in response to first and second control signals.

First claim

What is claimed is:

1 . A data input circuit of a semiconductor apparatus, comprising:
a plurality of parallelizing units corresponding to a plurality of input/output pads in a one-to-one manner; and a data control block configured to transmit serial test data, which is input through less than all of the plurality of input/output pads, to the plurality of parallelizing units in response to a first control signal and a second control signal.

2 . The data input circuit of a semiconductor apparatus according to claim 1 , further comprising:
a peripheral circuit/core block configured to receive parallel data from the plurality of parallelizing units and to store parallel data in response to a write command, and to output the data previously stored through the plurality of input/output pads in response to a read command.

3 . The data input circuit of a semiconductor apparatus according to claim 1 , wherein the data control block is configured to transmit serial normal data to the plurality of parallelizing units in response to the first and second control signals,
wherein the serial normal data is input through the plurality of input/output pads.

4 . The data input circuit of a semiconductor apparatus according to claim 1 , wherein the data control block comprises:
a plurality of first data processing units coupled to less than all of the plurality of input/output pads; and a plurality of second data processing units coupled to remaining input/output pads, wherein the input/output pads coupled with the second data processing units are different from the input/output pads coupled with the first data processing units.

5 . The data input circuit of a semiconductor apparatus according to claim 4 , wherein the plurality of first data processing units are configured to generate first output signals and second output signals by using the serial test data, and to transmit the first output signals to less than all of the plurality of parallelizing units corresponding to the less than all of the plurality of input/output pads.

6 . The data input circuit of a semiconductor apparatus according to claim 4 , wherein the plurality of second data processing units are configured to generate third output signals by using the second output signals, and to transmit the third output signals to the remaining parallelizing units, except for the less than all of the plurality of parallelizing units.

7 . The data input circuit of a semiconductor apparatus according to claim 4 , wherein each of the plurality of first data processing units comprises:
a first multiplexer configured to output a signal input through an input/output pad connected to a first input terminal, or a signal input through a second input terminal as a first output signal in response to the first control signal; and a second multiplexer configured to output a signal input through the input/output pad connected to a first input terminal, or a signal input through a second input terminal as a second output signal in response to the second control signal.

8 . The data input circuit of a semiconductor apparatus according to claim 7 , wherein the second input terminal of the second multiplexer is coupled to a ground terminal.

9 . The data input circuit of a semiconductor apparatus according to claim 7 , wherein each of the plurality of second data processing units comprises:
a multiplexer configured to output a signal input through an input/output pad connected to a first input terminal, or the second output signal input through a second input terminal as a third output signal in response to the first control signal.

10 . A data input circuit of a semiconductor apparatus, comprising:
a plurality of parallelizing units corresponding to a plurality of input/output pads in a one-to-one manner; and a data control block configured to convert a pattern of serial test data in response to a first control signal and a second control signal, and to transmit the serial test data to the plurality of parallelizing units, wherein the serial test data is input through one of the plurality of input/output pads.

11 . The data input circuit of a semiconductor apparatus according to claim 10 , further comprising:
a peripheral circuit/core block configured to receive parallel data from the plurality of parallelizing units and to store parallel data in response to a write command, and to output the data previously stored through the plurality of input/output pads in response to a read command.

12 . The data input circuit of a semiconductor apparatus according to claim 10 , wherein the data control block is configured to transmit serial normal data to the plurality of parallelizing units in response to the first and second control signals,
wherein the serial normal data is input through the plurality of input/output pads.

13 . The data input circuit of a semiconductor apparatus according to claim 10 , wherein the data control block comprises:
a pattern conversion unit configured to convert the pattern of the serial test data, and to generate plural test data having patterns different from each other; a plurality of first data processing units configured to be coupled to less than all of the plurality of input/output pads and to generate first output signals and second output signals by using the plural test data; and a plurality of second data processing units configured to be coupled to remaining input/output pads, and to generate third output signals by using the second output signals, wherein the serial test data is input through the one of the plurality of input/output pads, and wherein the input/output pads coupled with the second data processing units are different from the input/output pads coupled with the first data processing units.

14 . The data input circuit of a semiconductor apparatus according to claim 13 , further comprising:
a switch coupled between the pattern conversion unit and the input/output unit of where the serial test data is received, wherein the switch transmits the serial test data received through the input/output unit of where the serial test data is received to the pattern conversion unit in response to a third control signal.

15 . The data input circuit of a semiconductor apparatus according to claim 13 , wherein the plurality of first data processing units are configured to transmit the first output signals to less than all of the plurality of parallelizing units corresponding to the part of the plurality of input/output pads.

16 . The data input circuit of a semiconductor apparatus according to claim 13 , wherein the plurality of second data processing units are configured to transmit the third output signals to the remaining parallelizing units, except for the less than all of the plurality of parallelizing units.

17 . The data input circuit of a semiconductor apparatus according to claim 13 , wherein each of the plurality of first data processing units comprises:
a first multiplexer configured to output a signal input through an input/output pad connected to a first input terminal, or a signal input through a second input terminal as a first output signal in response to the first control signal; and a second multiplexer configured to output a signal input through the input/output pad connected to a first input terminal, or one of the plural test data input through a second input terminal as a second output signal in response to the second control signal.

18 . The data input circuit of a semiconductor apparatus according to claim 17 , wherein

Assignees

• Sk Hynix Inc

Inventors

• Choi Joon Woo
• Baek Chang Ki

Classifications

• G06F13/102 Primary

  where the program performs an interfacing function, e.g. device driver (G06F13/105 takes precedence; contention policies within device drivers G06F9/4881; scheduling within device drivers G06F9/52) · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F11/273

  Tester hardware, i.e. output processing circuits {(G06F11/263 takes precedence)} · CPC title