Methods of forming stressed channel regions for a finfet semiconductor device and the resulting device
US-2015255608-A1 · Sep 10, 2015 · US
Recessed channel fin device with raised source and drain regions
US2015340468A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2015340468-A1 |
| Application number | US-201414283721-A |
| Country | US |
| Kind code | A1 |
| Filing date | May 21, 2014 |
| Priority date | May 21, 2014 |
| Publication date | Nov 26, 2015 |
| Grant date | — |
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Abstract
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A method includes forming at least one fin in a semiconductor substrate. A sacrificial gate structure is formed around a first portion of the at least one fin. Sidewall spacers are formed adjacent the sacrificial gate structure. The sacrificial gate structure and spacers expose a second portion of the at least one fin. An epitaxial material is formed on the exposed second portion. At least one process operation is performed to remove the sacrificial gate structure and thereby define a gate cavity between the spacers that exposes the first portion of the at least one fin. The first portion of the at least one fin is recessed to a first height less than a second height of the second portion of the at least one fin. A replacement gate structure is formed within the gate cavity above the recessed first portion of the at least one fin.
First claim
Opening claim text (preview).
What is claimed: 1 . A method, comprising: forming at least one fin in a semiconductor substrate; forming a sacrificial gate structure around a first portion of said at least one fin; forming sidewall spacers adjacent said sacrificial gate structure, said sacrificial gate structure and said spacers exposing a second portion of said at least one fin; forming an epitaxial material on said exposed second portion of said at least one fin; performing at least one process oper…
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Classifications
Electricity · mapped topic
- H10D30/024Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US2015340468A1 cover?
- A method includes forming at least one fin in a semiconductor substrate. A sacrificial gate structure is formed around a first portion of the at least one fin. Sidewall spacers are formed adjacent the sacrificial gate structure. The sacrificial gate structure and spacers expose a second portion of the at least one fin. An epitaxial material is formed on the exposed second portion. At least one …
- Who is the assignee on this patent?
- Globalfoundries Inc
- What technology area does this patent fall under?
- Primary CPC classification H10D30/024. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Nov 26 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).