Process for bonding two substrates
US-8999090-B2 · Apr 7, 2015 · US
Gas-controlled bonding platform for edge defect reduction during wafer bonding
US2015318260A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2015318260-A1 |
| Application number | US-201414269457-A |
| Country | US |
| Kind code | A1 |
| Filing date | May 5, 2014 |
| Priority date | May 5, 2014 |
| Publication date | Nov 5, 2015 |
| Grant date | — |
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Abstract
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A wafer bonding method includes placing a top wafer on a top bonding framework including a plurality of outlet holes around a periphery of the top bonding framework. A bottom wafer is placed on a bottom bonding framework that includes a plurality of inlet holes around a periphery of the bottom bonding framework. The top bonding framework is in overlapping relation to the bottom bonding framework such that a gap exist between the top wafer and the bottom wafer. A gas stream is circulated through the gap between the top wafer and the bottom wafer entering the gap through one or more of the plurality of inlet holes and exiting the gap through one or more of the plurality of outlet holes. The gas stream replaces any existing ambient moisture from the gap between the top wafer and the bottom wafer.
First claim
Opening claim text (preview).
1 . A wafer bonding method, the method comprising: placing a top wafer on a top bonding framework, the top bonding framework including a plurality of outlet holes around a periphery of the top bonding framework; placing a bottom wafer on a bottom bonding framework, the bottom bonding framework including a plurality of inlet holes around a periphery of the bottom bonding framework; wherein the top bonding framework is in overlapping relation to the bottom bonding framework such that a gap ex…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US2015318260A1 cover?
- A wafer bonding method includes placing a top wafer on a top bonding framework including a plurality of outlet holes around a periphery of the top bonding framework. A bottom wafer is placed on a bottom bonding framework that includes a plurality of inlet holes around a periphery of the bottom bonding framework. The top bonding framework is in overlapping relation to the bottom bonding framewor…
- Who is the assignee on this patent?
- IBM
- What technology area does this patent fall under?
- Primary CPC classification H10P72/0428. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Nov 05 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).