Successive approximation analog-to-digital converters and methods using shift voltage to support oversampling

Patent metadata

Field	Value
Publication number	US-2015303938-A1
Application number	US-201514690881-A
Country	US
Kind code	A1
Filing date	Apr 20, 2015
Priority date	Apr 21, 2014
Publication date	Oct 22, 2015
Grant date	—

Abstract

An analog-to-digital converter includes a digital-to-analog converter comprising a capacitor divider network comprising a plurality of dividing capacitors and a dummy capacitor. The digital-to-analog converter is configured to selectively apply an input voltage and a reference voltage to the dividing capacitors and to selectively apply the input voltage and a shift voltage to the dummy capacitor. The analog-to-digital converter further includes a comparison circuit configured to compare an output of the capacitor divider network and a common mode voltage and a shift voltage generator circuit configured to generate the shift voltage. The shift voltage generator circuit may be configured to vary the shift voltage for different samples of the input voltage. For example, the shift voltage generator circuit may be configured to change the shift voltage for succeeding samples by an amount corresponding to 1/(2̂M) times the reference voltage to support 2̂M oversampling of the input voltage.

First claim

What is claimed is:

1 . An analog-to-digital converter comprising:
a digital-to-analog converter comprising a capacitor divider network comprising a plurality of dividing capacitors and a dummy capacitor, the digital-to-analog converter configured to selectively apply an input voltage and a reference voltage to the dividing capacitors and to selectively apply the input voltage and a shift voltage to the dummy capacitor; a comparison circuit configured to compare an output of the capacitor divider network and a common mode voltage; and a shift voltage generator circuit configured to generate the shift voltage.

2 . The analog-to-digital converter of claim 1 , wherein the shift voltage generator circuit is configured to vary the shift voltage for different samples of the input voltage.

3 . The analog-to-digital converter of claim 2 , wherein the shift voltage generator circuit is configured to change the shift voltage for succeeding samples by an amount corresponding to 1/(2̂M) times the reference voltage to support 2̂M oversampling of the input voltage.

4 . The analog-to-digital converter of claim 1 , wherein respective ones of the dividing capacitors correspond to respective bits of a digital output of the analog-to-digital converter and wherein the dummy capacitor has a capacitance substantially the same as a capacitance of a one of the dividing capacitors corresponding to a least significant bit (LSB) of the digital output.

5 . The analog-to-digital converter of claim 1 , wherein the digital-to-analog converter comprises a plurality of multiplexers, respective ones of which are coupled to respective ones of the dividing capacitors and the dummy capacitor.

6 . The analog-to-digital converter of claim 5 , further comprising a register coupled to an output of the comparison circuit and configured to provide respective control signals to respective ones of the multiplexers.

7 . The analog-to-digital converter of claim 1 , wherein the capacitor divider network is a split capacitor divider circuit comprising a bridge capacitor coupling two groups of the dividing capacitors.

8 . The analog-to-digital converter of claim 1 , wherein the digital-to-analog converter is a multi-stage digital-to-analog converter configured to selectively apply first and second reference voltages to the dividing capacitors for respective first and second groups of bits of a digital output of the analog-to-digital converter.

9 . The analog-to-digital converter of claim 8 :
wherein the first reference voltage comprises a first lower reference voltage and a first upper reference voltage that is higher than the first lower reference voltage by a level of the first reference voltage; and wherein the second reference voltage comprises a second lower reference voltage that is higher than the first lower reference voltage by a level that is obtained by dividing the level of the first reference voltage by 2̂(N/2) and a second upper reference voltage that is higher than the first upper reference voltage by a level that is obtained by dividing the level of the first reference voltage by 2̂(N/2), wherein N is a number of bits of the digital output.

10 . The analog-to-digital converter of claim 9 , wherein if one of the upper N/2 bits of the input voltage is determined “0” as the result of the comparison performed by the comparison circuit, the second lower reference voltage is applied to the dividing capacitor that corresponds to “0” when the lower N/2 bits of the input voltage are determined.

11 . The analog-to-digital converter of claim 12 , wherein if one of the upper N/2 bits of the input voltage is determined “1” as the result of the comparison performed by the comparison circuit, the second upper reference voltage is applied to the dividing capacitor that corresponds to “1” when the lower N/2 bits of the input voltage are determined.

12 . An analog-to-digital conversion method comprising:
applying a first voltage sample to dividing capacitors and a dummy capacitor of a capacitor divider network of a digital-to-analog converter; applying a first shift voltage to the dummy capacitor; sequentially applying a reference voltage to respective ones of the dividing capacitors and comparing corresponding respective outputs of the capacitor divider network to a common mode voltage to generate a first multi-bit digital output value; applying a second voltage sample to dividing capacitors and a dummy capacitor of a capacitor divider network of a digital-to-analog converter; applying a second shift voltage different from the first shift voltage to the dummy capacitor; and sequentially applying the reference voltage to respective ones of the dividing capacitors and comparing corresponding respective outputs of the capacitor divider network to a common mode voltage to generate a second multi-bit digital output value.

13 . The method of claim 12 , wherein the second shift voltage differs from the first shift voltage by an amount corresponding to 1/(2̂M) times the reference voltage to support 2̂M oversampling.

14 . The method of claim 12 , wherein respective ones of the dividing capacitors correspond to respective bits of a digital output of the analog-to-digital converter and wherein the dummy capacitor has a capacitance substantially the same as a capacitance of a one of the dividing capacitors corresponding to a least significant bit (LSB).

15 . An analog-to-digital converter comprising:
a digital-to-analog converter comprising a capacitor divider network and configured to selectively apply an input voltage, a reference voltage and a shift voltage to the capacitor divider network; a comparison circuit configured to compare an output of the capacitor divider network and a common mode voltage to generate a digital output; and a shift voltage generator circuit configured to generate the shift voltage.

16 . The analog-to-digital converter of claim 15 , wherein the shift voltage generator circuit is configured to vary the shift voltage for different samples of the input voltage.

17 . The analog-to-digital converter of claim 16 , wherein the shift voltage generator circuit is configured to change the shift voltage for succeeding samples of the input voltage by an amount corresponding to 1/(2̂M) times the reference voltage to support 2̂M oversampling of the input voltage.

18 . The analog-to-digital converter of claim 15 , wherein the capacitor divider network comprises a dummy capacitor and respective dividing capacitors corresponding to respective bits of the digital output and wherein the digital-to-analog converter is configured to selectively apply the input voltage and the reference voltage to the dividing capacitors and to selectively apply the input voltage and the shift voltage to the dummy capacitor.

19 . The analog-to-digital converter of claim 18 , wherein the dummy capacitor has a capacitance substantially the same as a capacitance of one of the dividing capacitors corresponding to an LSB of the digital output.

20 . The analog-to-digital converter of claim 15 , further comprising a register coupled an output of the comparison circuit and to an output of the digital-to-analog converter.

Assignees

• Samsung Electronics Co Ltd
• Iucf Hyu

Inventors

• Kim Yun-Jung
• Kim Jong-Boo
• Kwon Oh-Kyong

Classifications

• H03M1/121

  Interleaved, i.e. using multiple converters or converter parts for one channel · CPC title

• H03M1/468 Primary

  in which the input S/H circuit is merged with the feedback DAC array · CPC title

• H03M1/804

  with charge redistribution · CPC title

• H03M1/201

  by dithering · CPC title

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title