Semiconductor device
US-8941152-B1 · Jan 27, 2015 · US
Semiconductor device with through molding vias
US2015166329A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2015166329-A1 |
| Application number | US-201314107034-A |
| Country | US |
| Kind code | A1 |
| Filing date | Dec 16, 2013 |
| Priority date | Dec 16, 2013 |
| Publication date | Jun 18, 2015 |
| Grant date | — |
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Abstract
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A method of forming a semiconductor device having through molding vias comprises eutectic bonding a capping wafer and a base wafer to form a wafer package. The base wafer comprises a first chip package portion, a second chip package portion, and a third chip package portion. The capping wafer comprises a plurality of isolation trenches and a plurality of separation trenches having a depth greater than the isolation trenches with respect to a same surface of the capping wafer. The method also comprises removing a portion of the capping wafer exposing a first chip package portion contact, a second chip package portion contact, and a third chip package portion contact. The method further comprises separating the wafer package to separate the wafer package into a first chip package, a second chip package, and a third chip package.
First claim
Opening claim text (preview).
What is claimed is: 1 . A method of forming a semiconductor device comprising: eutectic bonding a capping wafer and a base wafer to form a wafer package, wherein the base wafer comprises a first chip package portion, a second chip package portion, and a third chip package portion, and the capping wafer comprises a plurality of isolation trenches, the plurality of isolation trenches being configured to substantially align with a corresponding trench region of one of the first…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US2015166329A1 cover?
- A method of forming a semiconductor device having through molding vias comprises eutectic bonding a capping wafer and a base wafer to form a wafer package. The base wafer comprises a first chip package portion, a second chip package portion, and a third chip package portion. The capping wafer comprises a plurality of isolation trenches and a plurality of separation trenches having a depth great…
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg
- What technology area does this patent fall under?
- Primary CPC classification B81C1/00301. Mapped technology areas include Operations & Transport.
- When was this patent published?
- Publication date Thu Jun 18 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).