Semiconductor device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-2015097189-A1
Application number	US-201414568227-A
Country	US
Kind code	A1
Filing date	Dec 12, 2014
Priority date	Jun 11, 2010
Publication date	Apr 9, 2015
Grant date	—

Abstract

A semiconductor device manufacturing method of an embodiment includes the steps of: forming a first insulating layer on a semiconductor substrate; forming on the first insulating layer an amorphous or polycrystalline semiconductor layer having a narrow portion; forming on the semiconductor layer a second insulating layer having a thermal expansion coefficient larger than that of the semiconductor layer; performing thermal treatment; removing the second insulating layer; forming a gate insulating film on the side faces of the narrow portion; forming a gate electrode on the gate insulating film; and forming a source-drain region in the semiconductor layer.

First claim

1 - 11 . (canceled)

12 . A semiconductor device manufacturing method, comprising:
forming a first insulating layer on a semiconductor substrate; forming a gate electrode layer on the first insulating layer; forming a second insulating layer on the gate electrode layer; forming a groove penetrating through the second insulating layer, the gate electrode layer and the first insulating layer; forming a third insulating layer on the inner side face of the groove; forming an amorphous or polycrystalline semiconductor layer on the inner side face of the third insulating layer; forming on the inner side face of the semiconductor layer a fourth insulating layer having a thermal expansion coefficient larger than a thermal expansion coefficient of the semiconductor layer; performing thermal treatment; and removing the third insulating layer.

13 . The method according to claim 12 , further comprising between the forming the groove and the forming the third insulating layer:
forming a fifth insulating layer on the inner side face of the groove; and forming a charge-storage insulating layer on the inner side face of the fifth insulating layer.

14 . The method according to claim 12 , wherein the semiconductor layer includes silicon.

15 . The method according to claim 12 , wherein the fourth insulating layer includes a silicon nitride layer.

16 - 18 . (canceled)

19 . A semiconductor device, comprising:
a first insulating layer; a gate electrode layer provided on the first insulating layer; a second insulating layer provided on the gate electrode layer; a columnar inner insulating layer extending in a stacking direction of the first insulating layer, the gate electrode layer and the second insulating layer; a third insulating layer provided between the gate electrode layer and the columnar inner insulating layer; and a polycrystalline semiconductor layer provided between the third insulating layer and the columnar inner insulating layer, wherein a crystal lattice spacing of the polycrystalline semiconductor layer in the stacking direction is larger than a crystal lattice spacing in a non-distorted state.

20 . The device according to claim 19 , further comprising:
a charge-storage insulating layer provided between the gate electrode layer and the third insulating layer; and a fourth insulating layer provided between the gate electrode layer and the charge-storage insulating layer.

21 . The device according to claim 19 , wherein the polycrystalline semiconductor layer includes silicon.

22 . The device according to claim 19 , further comprising:
a source region electrically connected to one end of the polycrystalline semiconductor layer; and a drain region electrically connected to other end of the polycrystalline semiconductor layer.

23 . The device according to claim 19 , wherein the third insulating layer includes at least one of the group consisting of a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer and a hafnium oxide layer.

24 . The device according to claim 20 , wherein the charge-storage insulating layer includes at least one of the group consisting of a silicon nitride layer and a hafnium oxide layer.

25 . The device according to claim 20 , wherein the fourth insulating layer includes at least one of the group consisting of a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer and a hafnium oxide layer.

26 . The device according to claim 19 , wherein the tensile strain is induced in the polycrystalline semiconductor layer in the stacking direction.

Assignees

• Toshiba Kk

Inventors

• Saitoh Masumi
• Numata Toshinori
• Nakabayashi Yukio

Classifications

• B82Y10/00

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  the components including FinFETs · CPC title

• H10D84/85

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