Method and layout for detecting die cracks

Patent metadata

Field	Value
Publication number	US-2015048373-A1
Application number	US-201414527756-A
Country	US
Kind code	A1
Filing date	Oct 29, 2014
Priority date	Jul 4, 2013
Publication date	Feb 19, 2015
Grant date	—

Abstract

A method of detecting a crack in a semiconductor die is provided. The method includes the following steps. A semiconductor die having an outer edge is provided, wherein a conductive feature is formed on semiconductor die along the outer edge. The conductive feature is biased, and a leakage current of the semiconductor die is measured, such that the crack propagating in the semiconductor the is detected. A semiconductor the with a layout for detecting a die crack and the method of manufacturing it are also provided. The semiconductor the includes a semiconductor the having an outer edge, and a conductive feature on the semiconductor die along the outer edge. The conductive feature is configured to be biased by an external pin.

First claim

What is claimed is:

1 . A semiconductor die with a layout for detecting a die crack, comprising:
a semiconductor die having an outer edge; and a conductive feature on the semiconductor die along the outer edge, wherein the conductive feature is configured to be biased by an external pin.

2 . The semiconductor die of claim 1 , wherein the semiconductor die comprises a off-die barrier structure around the perimeter of the outer edge.

3 . The method of claim 1 , wherein the semiconductor die comprise two adjacent conductive paths around the perimeter, wherein an outer conductive path is an off-die barrier structure, and an inner conductive path is an elevated voltage bus for electrical fuse operations.

4 . The semiconductor die of claim 1 , wherein the conductive feature is a metal line.

5 . The semiconductor die of claim 4 wherein the metal line is extended from a bus of the semiconductor die.

6 . The semiconductor die of claim 5 , wherein the bus is a grounded bus.

Assignees

• Nanya Technology Corp

Inventors

• Veches Anthony David

Classifications

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H01L22/32 Primary

  Electricity · mapped topic

• G01R31/2644 Primary

  Adaptations of individual semiconductor devices to facilitate the testing thereof · CPC title

• G01R31/2831

  Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates (G01R31/318511 takes precedence; testing during manufacture H10P74/00) · CPC title