Sensor, clock frequency adjusting system and method thereof

Patent metadata

Field	Value
Publication number	US-2015035754-A1
Application number	US-201313953800-A
Country	US
Kind code	A1
Filing date	Jul 30, 2013
Priority date	Jul 30, 2013
Publication date	Feb 5, 2015
Grant date	—

Abstract

A clock frequency adjusting system is disclosed. The clock frequency adjusting system includes a sensing clock generating unit, a frequency-dividing unit and a controller. The frequency-dividing unit makes frequency of the sensing clock signal be divided by a frequency-dividing modulus and then outputs a clock calibration signal. The controller includes a period counter and a frequency adjusting unit. The period counter samples the clock calibration signal through the external clock signal so as to acquire a second count value. The frequency adjusting unit calculates a frequency difference data between the clock calibration signal and the predetermined clock signal according to the first count value and the second count value, and determines a number of adjustment according to the frequency difference data and a step adjusting frequency so as to output a clock adjusting signal to the sensing clock unit to adjust frequency of the sensing clock signal.

First claim

What is claimed is:

1 . A clock frequency adjusting system, comprising:
a sensing clock generating unit, generating a sensing clock signal; a frequency-dividing unit, electrically connected to the sensing clock generating unit, the frequency-dividing unit receiving the sensing clock signal and making frequency of the sensing clock signal be divided by a frequency-dividing modulus and then outputting a clock calibration signal, wherein the frequency-dividing modulus is a positive integer; and a controller, electrically connected to the frequency-dividing unit, the controller having a first count value, wherein the first count value is equal to frequency of an external clock signal divided by frequency of a predetermined clock signal, the controller comprising: a period counter, electrically connected to the frequency-dividing unit, the period counter receiving the external clock signal and the clock calibration signal, and sampling the clock calibration signal through the external clock signal so as to acquire a second count value; and a frequency adjusting unit, electrically connected to the period counter, the frequency adjusting unit calculating a frequency difference data between the clock calibration signal and the predetermined clock signal according to the first count value and the second count value, and determining a number of adjustment according to the frequency difference data and a step adjusting frequency so as to output a clock adjusting signal to the sensing clock unit to adjust frequency of the sensing clock signal.

2 . The clock frequency adjusting system according to claim 1 , wherein the frequency adjusting unit is configured to subtract reciprocal of the second count value from reciprocal of the first count value and then make result be multiplied by the frequency-dividing modulus so as to acquire the frequency difference data, and makes frequency of the external clock signal be divided by the step adjusting frequency so as to acquire a step adjusting data.

3 . The clock frequency adjusting system according to claim 2 , wherein the frequency adjusting unit makes the frequency difference data be multiplied by the step adjusting data so as to acquire the number of adjustment, wherein the number of adjustment is a positive integer.

4 . The clock frequency adjusting system according to claim 1 , wherein the frequency adjusting unit transmits the clock adjusting signal to the sensing clock generating unit so as to once adjust frequency of the sensing clock signal according to the frequency difference data and the step adjusting frequency.

5 . The clock frequency adjusting system according to claim 1 , wherein the frequency adjusting unit transmits the clock adjusting signal to the sensing clock generating unit so as to gradually adjust frequency of the sensing clock signal according to the number of adjustment and the step adjusting frequency.

6 . The clock frequency adjusting system according to claim 1 , wherein the second count value is equal to frequency of an external clock signal divided by frequency of the clock calibration signal.

7 . The clock frequency adjusting system according to claim 1 , wherein the controller further comprising:
a programmable memory unit, electrically connected to the frequency adjusting unit, the programmable memory unit storing the frequency-dividing modulus, the first count value, the step adjusting frequency and the number of adjustment.

8 . The clock frequency adjusting system according to claim 1 , further comprising:
an image capture unit, electrically connected to the sensing clock generating unit, the image capture unit receiving the sensing clock signal and accordingly capturing a surface image, wherein the image capture unit has a predetermined frame rate, and the predetermined frame rate is corresponding to frequency of the predetermined clock signal.

9 . A sensor, used for a mouse, the sensor comprising:
a sensing clock generating unit, generating a sensing clock signal; a frequency-dividing unit, electrically connected to the sensing clock generating unit, the frequency-dividing unit receiving the sensing clock signal and making frequency of the sensing clock signal divided by a frequency-dividing modulus and then outputting a clock calibration signal, wherein the frequency-dividing modulus is a positive integer; and an image capture unit, electrically connected to the sensing clock generating unit, the image capture unit receiving the sensing clock signal and accordingly capturing a surface image, wherein the image capture unit has a predetermined frame rate, and the predetermined frame rate is corresponding to frequency of the predetermined clock signal, wherein the frequency-dividing unit is electrically connected to a controller, the controller has a first count value, and the first count value is equal to frequency of an external clock signal divided by frequency of a predetermined clock signal, the controller comprising: a period counter, electrically connected to the frequency-dividing unit, the period counter receiving the external clock signal and the clock calibration signal, and sampling the clock calibration signal through the external clock signal so as to acquire a second count value; and a frequency adjusting unit, electrically connected to the period counter, the frequency adjusting unit calculating a frequency difference data between the clock calibration signal and the predetermined clock signal according to the first count value and the second count value, and determining a number of adjustment according to the frequency difference data and a step adjusting frequency so as to output a clock adjusting signal to the sensing clock unit to adjust frequency of the sensing clock signal.

10 . The sensor according to claim 9 , wherein the frequency adjusting unit is configured to subtract reciprocal of the second count value from reciprocal of the first count value and then make result be multiplied by the frequency-dividing modulus so as to acquire the frequency difference data, and makes frequency of the external clock signal be divided by the step adjusting frequency so as to acquire a step adjusting data.

11 . The sensor according to claim 10 , wherein the frequency adjusting unit makes the frequency difference data be multiplied by the step adjusting data so as to acquire the number of adjustment, wherein the number of adjustment is a positive integer.

12 . The sensor according to claim 9 , wherein the frequency adjusting unit transmits the clock adjusting signal to the sensing clock generating unit so as to adjust frequency of the sensing clock signal according to the frequency difference data and the step adjusting frequency.

13 . The sensor according to claim 9 , wherein the frequency adjusting unit transmits the clock adjusting signal to the sensing clock generating unit so as to adjust frequency of the sensing clock signal according to the number of adjustment and the step adjusting frequency.

14 . The sensor according to claim 9 , wherein the second count value is equal to frequency of an external clock signal divided by frequency of the clock calibration signal.

15 . The sensor according to claim 9 , wherein the controller further comprising:
a programmable memory unit, electrically connected to the frequency adjusting unit, the programmable memory unit storing the frequency-dividing modulus, the first count value, the step adjusting frequency and the number of adjustment.

16 . A clock frequency adjusting method, used for a clock frequency adjusting system, the clock frequency adj

Assignees

• Pixart Imaging Inc

Inventors

• Lim Kevin Len-Li

Classifications

• G06F1/12 Primary

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• G06F3/03543 Primary

  Mice or pucks (G06F3/03541 takes precedence) · CPC title

• H03L7/08

  Details of the phase-locked loop · CPC title

• H03L7/00

  Automatic control of frequency or phase; Synchronisation · CPC title

• G06F3/038

  Control and interface arrangements therefor, e.g. drivers or device-embedded control circuitry · CPC title