Thin film transistors having ferroelectric material for providing pixel compensation

Patent metadata

Field	Value
Publication number	US-12598807-B2
Application number	US-202217882623-A
Country	US
Kind code	B2
Filing date	Aug 8, 2022
Priority date	Dec 9, 2021
Publication date	Apr 7, 2026
Grant date	Apr 7, 2026

Abstract

An active device substrate includes a substrate, a first semiconductor device and a second semiconductor device. The first semiconductor device and the second semiconductor device are disposed above the substrate. The first semiconductor device includes a first gate, a first semiconductor layer, a first source and a first drain. A first gate dielectric structure is sandwiched between the first gate and the first semiconductor layer. The first gate dielectric structure includes a stack of a portion of a gate dielectric layer and a portion of a ferroelectric material layer. The second semiconductor device is electrically connected to the first semiconductor device and includes a second gate, a second semiconductor layer, a second source and a second drain. Another part of the ferroelectric material layer is sandwiched between the second gate and the second semiconductor layer.

First claim

What is claimed is:

1 . An active device substrate, comprising:
a substrate; a first semiconductor device, disposed above the substrate, wherein the first semiconductor device comprises:
a first gate and a first semiconductor layer, wherein a gate dielectric structure is sandwiched between the first gate and the first semiconductor layer, wherein the gate dielectric structure comprises a stack of a portion of a gate dielectric layer and a portion of a ferroelectric material layer; and
a first source and a first drain, electrically connected to the first semiconductor layer; and
a second semiconductor device, disposed above the substrate, and electrically connected to the first semiconductor device, wherein the second semiconductor device comprises:
a second gate and a second semiconductor layer, wherein another portion of the ferroelectric material layer is filled into an opening of the gate dielectric layer, and the another portion of the ferroelectric material layer is sandwiched between the second gate and the second semiconductor layer; and
a second source and a second drain, electrically connected to the second semiconductor layer.

2 . The active device substrate of claim 1 , wherein a distance between the first gate and the first semiconductor layer is greater than a distance between the second gate and the second semiconductor layer, wherein the ferroelectric material layer is in contact with the first gate, the second gate and the second semiconductor layer, and the ferroelectric material layer is separated from the first semiconductor layer.

3 . The active device substrate of claim 1 , wherein the ferroelectric material layer is extending from between the first gate and the gate dielectric layer to between the second gate and the second semiconductor layer.

4 . The active device substrate of claim 1 , wherein the ferroelectric material layer is surrounding the first source, the first drain, the second source and the second drain.

5 . The active device substrate of claim 1 , wherein the first source, the first drain, the second source and the second drain are penetrating through the ferroelectric material layer.

6 . The active device substrate of claim 1 , wherein a sub-threshold swing of the first semiconductor device is less than 60 mV/dec.

7 . The active device substrate of claim 1 , wherein a material of the ferroelectric material layer comprises Ni x Mg y Zn 0.98-y O or Hf z Zr 1-z O 2 , wherein x is in a range from 0.01 to 0.05, y is in a range from 0.05 to 0.15, and z is in a range from 0.4 to 0.6.

8 . The active device substrate of claim 1 , wherein a thickness of the ferroelectric material layer is in a range from 5 nm to 50 nm, a thickness of the gate dielectric layer is in a range from 50 nm to 100 nm, and a length of the opening of the gate dielectric layer is less than a length of the second semiconductor layer.

9 . The active device substrate of claim 1 , further comprising:
a third semiconductor device, disposed above the substrate, and electrically connected to the second semiconductor device, wherein the third semiconductor device comprises:
a third gate and a third semiconductor layer, wherein another portion of the gate dielectric layer is sandwiched between the third gate and the third semiconductor layer; and
a third source and a third drain, electrically connected to the third semiconductor layer.

10 . The active device substrate of claim 9 , wherein the first drain is electrically connected to the second gate, and the third drain is electrically connected to the second source.

11 . A manufacturing method of an active device substrate, comprising:
forming a first semiconductor layer and a second semiconductor layer above a substrate; forming a gate dielectric layer on the first semiconductor layer, wherein the gate dielectric layer has an opening; forming a ferroelectric material layer on the gate dielectric layer and the second semiconductor layer; forming a first gate and a second gate on the ferroelectric material layer, wherein a gate dielectric structure is sandwiched between the first gate and the first semiconductor layer, wherein the gate dielectric structure comprises a stack of a portion of the gate dielectric layer and a portion of the ferroelectric material layer, wherein another portion of the ferroelectric material layer is sandwiched between the second gate and the second semiconductor layer, and the another portion of the ferroelectric material layer is filled into the opening of the gate dielectric layer; forming a first source and a first drain electrically connected to the first semiconductor layer; and forming a second source and a second drain electrically connected to the second semiconductor layer, wherein a first semiconductor device comprises the first gate, the first semiconductor layer, the gate dielectric structure, the first source and the first drain, and a second semiconductor device is electrically connected to the first semiconductor device and comprises the second gate, the second semiconductor layer, the another portion of the ferroelectric material layer, the second source and the second drain.

12 . The manufacturing method of the active device substrate of claim 11 , further comprising:
using the first gate and the second gate as a mask, performing a doping process on the first semiconductor layer and the second semiconductor layer.

13 . The manufacturing method of the active device substrate of claim 11 , wherein the another portion of the ferroelectric material layer is filled into the opening to contact the second semiconductor layer, the ferroelectric material layer is in contact with the first gate and the second gate, and the ferroelectric material layer is separated from the first semiconductor layer.

14 . The manufacturing method of the active device substrate of claim 11 , further comprising:
forming a third semiconductor layer above the substrate, wherein the first semiconductor layer, the second semiconductor layer and the third semiconductor layer are formed simultaneously; forming the gate dielectric layer on the third semiconductor layer; forming a third gate on the gate dielectric layer, wherein the first gate, the second gate and the third gate are formed simultaneously; and forming a third source and a third drain electrically connected to the third semiconductor layer, wherein the first source, the first drain, the second source, the second drain, the third source and the third drain are formed simultaneously.

Assignees

• Auo Corp

Inventors

• Fan Yang-Shun
• Huang Chen-Shuo

Classifications

• H10D30/0415

  of FETs having ferroelectric gate insulators · CPC title

• H10D30/701

  IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs · CPC title

• H10D86/021

  of multiple TFTs · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title