Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2019103493-A1
Application number	US-201816207081-A
Country	US
Kind code	A1
Filing date	Nov 30, 2018
Priority date	Nov 29, 2016
Publication date	Apr 4, 2019
Grant date	—

Abstract

A semiconductor device includes a memory circuit and a logic circuit. The memory circuit includes a word line, a bit line, a common line and a memory transistor having a gate coupled to the word line, a drain coupled to the bit line and a source coupled to the common line. The logic circuit includes a field effect transistor (FET) having a gate, a drain and a source. The memory transistor has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a first insulating layer and a first ferroelectric (FE) material layer. The FET has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a second insulating layer and a second FE material layer.

First claim

1 . A semiconductor device, comprising:
a memory field effect transistor having a gate, a drain, and a source; and a logic transistor having a gate, a drain and a source, wherein:
the gate of the memory field effect transistor comprises:
a first insulating layer disposed over a substrate;
a first ferroelectric material layer disposed over the first insulating layer; and
a first gate electrode layer disposed over the first ferroelectric material layer, and

the gate of the logic transistor comprises:
a second insulating layer disposed over the substrate;
a second ferroelectric material layer disposed over the second insulating layer; and
a second gate electrode layer disposed over the second ferroelectric material layer,
wherein a thickness of the first insulating layer is different from a thickness of the second insulating layer.

2 . A semiconductor device, comprising:
a memory field effect transistor having a gate, a drain, and a source; and a logic transistor having a gate, a drain and a source, wherein:
the gate of the memory field effect transistor comprises:
a first insulating layer disposed over a substrate;
a first ferroelectric material layer disposed over the first insulating layer; and
a first gate electrode layer disposed over the first ferroelectric material layer, and

the gate of the logic transistor comprises:
a second insulating layer disposed over the substrate;
a second ferroelectric material layer disposed over the second insulating layer; and
a second gate electrode layer disposed over the second ferroelectric material layer, and
wherein a thickness of the gate electrode layer of the memory transistor is different from a thickness of the gate electrode layer of the logic transistor.

3 . A semiconductor device, comprising:
a first field effect transistor having a gate, a drain, and a source; and a second field effect transistor having a gate, a drain and a source, wherein:
the gates of the first and second transistors each comprise:
an insulating layer disposed over a substrate;
a ferroelectric material layer disposed over the insulating layer; and
a gate electrode layer disposed over the ferroelectric material layer,
wherein the insulating layer of the first field effect transistor is thinner than the insulating layer of the second field effect transistor and the gate electrode layer of the first field effect transistor is thicker than the gate electrode layer of the second field effect transistor.

4 . The semiconductor device of claim 1 , wherein the first ferroelectric material layer and the second ferroelectric material layer are made of a same ferroelectric material and have a same thickness.

5 . The semiconductor device of claim 4 , wherein:
the same ferroelectric material is one of PGO, PZT, SBT, SBO, SBTO, SBTN, STO, BTO, BLT, LNO, YMnO 3 , ZrO 2 , zirconium silicate, ZrAlSiO, HfO 2 , hafnium silicate, HfAlO, LaAlO, lanthanum oxide, HfO 2 doped with Si, and Ta 2 O 5 .

6 . The semiconductor device of claim 1 , wherein a thickness of the first insulating layer is greater than a thickness of the second insulating layer.

7 . The semiconductor device of claim 1 , wherein a thickness of the first insulating layer is smaller than a thickness of the second insulating layer.

8 . The semiconductor device of claim 1 , wherein the first and second insulating layers are made of one or more layers of silicond oxide, silicon nitride, and silicon oxynitride.

9 . The semiconductor device of claim 1 , wherein the first gate electrode layer and the second gate electrode layer are made of polysilicon.

10 . The semiconductor device of claim 2 , wherein the first ferroelectric material layer and the second ferroelectric material layer are made of a same ferroelectric material and have a same thickness.

11 . The semiconductor device of claim 10 , wherein:
the same ferroelectric material is one of PGO, PZT, SBT, SBO, SBTO, SBTN, STO, BTO, BLT, LNO, YMnO 3 , ZrO 2 , zirconium silicate, ZrAlSiO, HfO 2 , hafnium silicate, HfAlO, LaAlO, lanthanum oxide, HfO 2 doped with Si, and Ta 2 O 5 .

12 . The semiconductor device of claim 2 , wherein a thickness of the first insulating layer is smaller than a thickness of the second insulating layer.

13 . The semiconductor device of claim 2 , further comprising:
a first conductive layer disposed over the first ferroelectric layer; and a second conductive layer disposed over the second ferroelectric layer.

14 . The semiconductor device of claim 13 , wherein the first and second conductive layers are made of one or more layers of TiN, TaN, Ti, and W.

15 . The semiconductor device of claim 2 , further comprising:
a first work function adjustment layer having a U-shape in cross section disposed over the first ferroelectric material layer; and a second work function adjustment layer having a U-shape in cross section disposed over the second ferroelectric material layer, wherein the first gate electrode layer is surrounded by the first work function adjustment layer and the second gate electrode layer is surrounded by the second work function adjustment layer.

16 . The semiconductor device of claim 3 , further comprising:
a work function adjustment layer having a U-shape in cross section disposed over each of the ferroelectric material layers; and wherein each of the gate electrode layers is surrounded by a corresponding work function adjustment layer.

17 . The semiconductor device of claim 3 , wherein a channel length of the second field effect transistor is greater than a channel length of the first field effect transistor.

18 . The semiconductor device of claim 3 , wherein the first field effect transistor is a logic transistor and the second field effect transistor is a memory transistor.

19 . The semiconductor device of claim 3 , wherein the first ferroelectric material layer and the second ferroelectric material layer are made of a same ferroelectric material and have a same thickness.

20 . The semiconductor device of claim 19 , wherein:
the same ferroelectric material is one of PGO, PZT, SBT, SBO, SBTO, BTN, STO, BTO, BLT, LNO, YMnO 3 , ZrO 2 , zirconium silicate, ZrAlSiO, HfO 2 , hafnium silicate, HfAlO, LaAlO, lanthanum oxide, HfO 2 doped with Si, and Ta 2 O 5 .

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tu Kuo-Chi
• Yang Jen-Sheng
• Shih Sheng-Hung
• Ong Tong-Chern
• Chu Wen-Ting

Classifications

• G11C11/2257

  Word-line or row circuits · CPC title

• G11C11/2273

  Reading or sensing circuits or methods · CPC title

• G11C11/223

  using MOS with ferroelectric gate insulating film · CPC title

• H01L29/6684

  Electricity · mapped topic

• H01L27/11592

  Electricity · mapped topic