Semiconductor devices

Patent metadata

Field	Value
Publication number	US-12598774-B2
Application number	US-202217935714-A
Country	US
Kind code	B2
Filing date	Sep 27, 2022
Priority date	Oct 12, 2021
Publication date	Apr 7, 2026
Grant date	Apr 7, 2026

Abstract

A semiconductor device includes active regions including first and second active regions parallel to each other and extending in a first direction, gate structures including first gate structures intersecting the first active region, extending in a second direction, and parallel to each other, and second gate structures intersecting the second active region, and opposite the first gate structures in the second direction, a gate isolation pattern between the first and second gate structures, a source/drain region on at least one side of the gate structures, and a common contact plug electrically connected to the source/drain region, wherein the gate isolation pattern includes a lower region and upper regions extending from the lower region in a third direction and spaced apart from each other in the first direction, wherein the upper regions are between the first and second gate structures.

First claim

What is claimed is:

1 . A semiconductor device comprising:
active regions including a first active region and a second active region parallel to each other on a substrate and extending in a first direction; a plurality of gate structures including first gate structures intersecting the first active region, extending in a second direction perpendicular to the first direction, and parallel to each other, and second gate structures intersecting the second active region, extending in the second direction, and opposite the first gate structures in the second direction, on the substrate; a gate isolation pattern between the first gate structures and the second gate structures; a source/drain region on at least one side of the plurality of gate structures and including a first source/drain region on the first active region and a second source/drain region on the second active region; and a common contact plug electrically connected to the first and second source/drain regions, wherein the gate isolation pattern includes:
a lower region; and
upper regions extending from the lower region in a third direction and spaced apart from each other in the first direction,
wherein the upper regions are between the first gate structures and the second gate structures, wherein a portion of the common contact plug is between the upper regions in the first direction, wherein each of the upper regions includes a third side surface in contact with the common contact plug and a fourth side surface opposite the third side surface, wherein the third side surface is coplanar with side surfaces of the first and second gate structures, wherein the first and second directions are parallel to an upper surface of the substrate, and wherein the third direction is perpendicular to the upper surface of the substrate.

2 . The semiconductor device of claim 1 , wherein each of the upper regions of the gate isolation pattern further includes a first side surface in contact with the first gate structures and a second side surface opposite the first side surface and in contact with the second gate structures.

3 . The semiconductor device of claim 2 , wherein a width of the first side surface is substantially equal to a width of each of the first gate structures in the first direction and a width of the second side surface is substantially equal to a width of each of the second gate structures in the first direction.

4 . The semiconductor device of claim 1 , wherein widths of the lower region and the upper regions of the gate isolation pattern are substantially equal in the second direction.

5 . The semiconductor device of claim 1 ,
wherein the upper regions of the gate isolation pattern overlap respective portions of the lower region of the gate isolation pattern in the third direction, and wherein an upper surface of the common contact plug is coplanar with respective upper surfaces of the upper regions of the gate isolation pattern.

6 . The semiconductor device of claim 1 , wherein the lower region and the upper regions of the gate isolation pattern provide a step difference along the first direction.

7 . The semiconductor device of claim 1 , wherein the gate isolation pattern includes at least one of a silicon nitride material, a silicon oxynitride material, a silicon oxide material, or a nitride material.

8 . The semiconductor device of claim 1 , wherein the common contact plug includes a lower surface comprising a first portion in contact with the first and second source/drain regions and a second portion in contact with the lower region of the gate isolation pattern.

9 . The semiconductor device of claim 8 , wherein the first portion of the lower surface is at a level lower than a level of the second portion of the lower surface.

10 . The semiconductor device of claim 1 , wherein the common contact plug is on a side surface of the lower region of the gate isolation pattern.

11 . The semiconductor device of claim 1 , further comprising:
a lower interlayer insulating layer on the active regions; and an upper interlayer insulating layer on the lower interlayer insulating layer, wherein an upper surface of the lower interlayer insulating layer is substantially coplanar with an upper surface of the lower region of the gate isolation pattern.

12 . The semiconductor device of claim 11 ,
wherein an upper end of the lower interlayer insulating layer includes impurities, and wherein a lower surface of the upper interlayer insulating layer is in contact with the upper surface of the lower interlayer insulating layer.

13 . A semiconductor device comprising:
a first active region and a second active region parallel to each other on a substrate and extending in a first direction; a device isolation layer between the first active region and the second active region; a plurality of gate structures including first gate structures intersecting the first active region, extending in a second direction perpendicular to the first direction, and parallel to each other, and second gate structures intersecting the second active region, extending in the second direction, and opposite the first gate structures in the second direction, on the substrate; a gate isolation pattern on the device isolation layer and including a lower region and upper regions spaced apart from each other in the first direction on the lower region; and a first source/drain region on the first active region and a second source/drain region on the second active region, wherein each of the upper regions of the gate isolation pattern includes a first side surface in contact with the first gate structures, a second side surface opposite the first side surface and in contact with the second gate structures, a third side surface, and a fourth side surface opposite the third side surface, and wherein a width of the lower region of the gate isolation pattern in the second direction is substantially equal to a width of each of the upper regions, and the lower region includes first portions overlapped by the upper regions and a second portion extending from the overlapped first portions in the first direction.

14 . The semiconductor device of claim 13 , further comprising:
a common contact plug electrically connected to the first and second source/drain regions, wherein the common contact plug includes a lower surface comprising a first portion in contact with the first and second source/drain regions and a second portion in contact with the lower region of the gate isolation pattern.

15 . The semiconductor device of claim 13 , further comprising:
a lower interlayer insulating layer on the first active region and the second active region; and an upper interlayer insulating layer on the lower interlayer insulating layer, wherein the upper interlayer insulating layer is on an upper surface of the lower region of the gate isolation pattern and a side surface of each of the upper regions of the gate isolation pattern.

16 . The semiconductor device of claim 13 , further comprising:
first channel layers stacked and spaced apart from each other in a third direction perpendicular to an upper surface of the substrate on the first active region; and second channel layers stacked and spaced apart from each other in the third direction on the second active region, wherein each of the plurality of gate structures includes a gate electrode, a gate spacer on opposite sides of the gate electrode, and a capping layer on the gate electrode and the gate spacer, and wherein the gate electrode surrounds the first and second channel l

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Jongchul
• Ra Hyonwook

Classifications

• H10D84/0188

  Manufacturing their isolation regions · CPC title

• H10D84/0186 Primary

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D64/017 Primary

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title