Method for Metal Gate Cut and Structure Thereof

Patent metadata

Field	Value
Publication number	US-2020006075-A1
Application number	US-201916366511-A
Country	US
Kind code	A1
Filing date	Mar 27, 2019
Priority date	Jun 29, 2018
Publication date	Jan 2, 2020
Grant date	—

Abstract

A method includes providing a structure having a substrate, first and second semiconductor fins extending from the substrate, and a dielectric fin between the first and second semiconductor fins; forming a temporary gate on top and sidewalls of the first and second semiconductor fins and the dielectric fin; forming gate spacers on sidewalls of the temporary gate; removing the temporary gate and a first portion of the dielectric fin between the gate spacers; forming a gate between the gate spacers and on top and sidewalls of the first and second semiconductor fins, wherein the dielectric fin is in physical contact with sidewalls of the gate; removing a second portion of the dielectric fin, thereby exposing the sidewalls of the gate; and performing an etching process to the gate through the exposed sidewalls of the gate, thereby separating the gate into a first gate segment and a second gate segment.

First claim

What is claimed is:

1 . A method, comprising:
providing a structure having a substrate, first and second semiconductor fins extending from the substrate, and a dielectric fin between the first and second semiconductor fins; forming a temporary gate on top and sidewalls of the first and second semiconductor fins and the dielectric fin; forming gate spacers on sidewalls of the temporary gate; removing the temporary gate and a first portion of the dielectric fin between the gate spacers; forming a gate between the gate spacers and on top and sidewalls of the first and second semiconductor fins, wherein the dielectric fin is in physical contact with sidewalls of the gate; removing a second portion of the dielectric fin, thereby exposing the sidewalls of the gate; and performing an etching process to the gate through the exposed sidewalls of the gate, thereby separating the gate into a first gate segment engaging the first semiconductor fin and a second gate segment engaging the second semiconductor fin.

2 . The method of claim 1 , further comprising:
forming a dielectric layer on the gate prior to the removing of the second portion of the dielectric fin.

3 . The method of claim 2 , wherein the forming of the dielectric layer includes:
recessing a top portion of the gate between the gate spacers; depositing the dielectric layer on top of the gate; and performing a chemical mechanical planarization process to recess the dielectric layer and expose a top surface of the dielectric fin.

4 . The method of claim 2 , wherein the dielectric layer and the gate spacers remain after the removing of the second portion of the dielectric fin.

5 . The method of claim 1 , wherein the etching process includes an anisotropic etching process.

6 . The method of claim 1 , wherein the etching process includes an isotropic etching process.

7 . The method of claim 1 , wherein the etching process includes a slanted plasma etching process.

8 . The method of claim 7 , wherein the etching process further includes a dry etching process following the slanted plasma etching process.

9 . The method of claim 1 , wherein the removing of the temporary gate and the first portion of the dielectric fin includes an anisotropic etching process such that other portions of the dielectric fin directly under the gate spacers remain.

10 . The method of claim 1 , wherein the dielectric fin has a smaller width than either of the first and second semiconductor fins.

11 . The method of claim 1 , wherein a topmost portion of the dielectric fin is higher than a topmost portion of the first and second semiconductor fins.

12 . The method of claim 1 , wherein the forming of the dielectric fin includes:
depositing an isolation structure over the substrate and on sidewalls of the first and second semiconductor fins, resulting in a trench between two portions of the isolation structure that are on two opposing sidewalls of the first and second semiconductor fins; and depositing the dielectric fin in the trench.

13 . A method, comprising:
providing a structure having a substrate and a dielectric fin projecting upwardly above the substrate; forming first and second spacer layers on the dielectric fin, wherein the first and second spacer layers have two opposing sidewalls; removing a portion of the dielectric fin between the two opposing sidewalls; forming a gate structure between the two opposing sidewalls; depositing a capping layer on the gate structure; removing another portion of the dielectric fin, thereby exposing sidewalls of the gate structure; and performing a lateral etching process on the sidewalls of the gate structure, thereby dividing the gate structure into two parts.

14 . The method of claim 13 , wherein the dielectric fin and the capping layer have different material compositions.

15 . The method of claim 14 , wherein the dielectric fin includes a nitride and the capping layer includes zirconium oxide.

16 . The method of claim 13 , wherein the lateral etching process includes a plasma etching utilizing HBr.

17 . The method of claim 13 , further comprising:
filling a dielectric material between the two parts of the gate structure while the capping layer remains above the gate structure.

18 . A semiconductor structure, comprising:
a substrate; a first semiconductor fin and a second semiconductor fin extending from the substrate; an isolation feature on the substrate and on sidewalls of the first and second semiconductor fins; a first high-k metal gate (HK MG) and a second HK MG, wherein the first HK MG is disposed over the first semiconductor fin, and the second HK MG is disposed over the second semiconductor fin; and a dielectric fin disposed between the first and second semiconductor fins, a middle portion of the dielectric fin being in physical contact with both the first HK MG and the second HK MG, a bottom portion of the dielectric fin being embedded in the isolation feature.

19 . The semiconductor structure of claim 18 , wherein the middle portion of the dielectric fin has a different material composition than other portions of the dielectric fin.

20 . The semiconductor structure of claim 18 , wherein the middle portion of the dielectric fin has a larger width than other portions of the dielectric fin.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Pei-Yu
• Lin zhi-chang
• Tsai Ching-Wei
• Cheng Kuan-Lun

Classifications

• H10P95/064

  the removal being chemical etching · CPC title

• H10P50/267

  using plasmas · CPC title

• H10D64/01326 Primary

  Aspects related to lithography, isolation or planarisation of the conductor · CPC title

• H01L27/0886

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic