Transistor with low leakage currents and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-12598765-B2
Application number	US-202418639993-A
Country	US
Kind code	B2
Filing date	Apr 19, 2024
Priority date	May 28, 2019
Publication date	Apr 7, 2026
Grant date	Apr 7, 2026

Abstract

A transistor with low leakage currents includes a substrate, a gate, spacers, pad dielectric layers, a source, and a drain. The gate is formed above a gate dielectric layer, wherein the gate dielectric layer has a first dielectric constant. The spacers have a second dielectric constant. The pad dielectric layers are formed under the spacers and having a third dielectric constant. The source and the drain are adjacent to the spacers and in two opposite directions of the gate. The first dielectric constant, the second dielectric constant, and the third dielectric constant are different from each other.

First claim

What is claimed is:

1 . A transistor, comprising:
a substrate with an original surface; a gate formed above a gate dielectric layer, wherein the gate dielectric layer directly contacts to the substrate; a first region coupled to one side of the gate, the first region comprising a first spacer, a first pad dielectric layer under the first spacer, and a first conductive region; and a second region coupled to another side of the gate, the second region comprising a second spacer, a second pad dielectric layer under the second spacer, and a second conductive region, wherein the first pad dielectric layer is separated from the second pad dielectric layer by the gate dielectric layer; wherein a first thickness of a first portion of the first pad dielectric layer close to the gate dielectric layer is less than a second thickness of a second portion of the first pad dielectric layer close to the first conductive region.

2 . The transistor of claim 1 , wherein a first thickness of a first portion of the second pad dielectric layer close to the gate dielectric layer is less than a second thickness of a second portion of the second pad dielectric layer close to the second conductive region.

3 . The transistor of claim 2 , wherein the first conductive region and the second conductive region are formed in a first concave of the substrate and a second concave of the substrate, respectively.

4 . The transistor of claim 3 , further comprising:
a first contact formed above the first conductive region; and a second contact formed above the second conductive region; wherein top surfaces of the first contact and the second contact are higher 5 nm to 400 nm than the top surface of the gate.

5 . The transistor of claim 1 , wherein the first region and the second region are asymmetric.

6 . The transistor of claim 1 , wherein the first conductive region at least extends downward from the original surface, and the second conductive region at least extends downward from the original surface.

Assignees

• Etron Tech Inc
• Invent And Collaboration Laboratory Pte Ltd

Inventors

• Lu chao-chun
• Ken Weng-Dah

Classifications

• H10D64/258

  characterised by the relative positions of the source or drain electrodes with respect to the gate electrode · CPC title

• H10D64/021 Primary

  using multiple gate spacer layers, e.g. bilayered sidewall spacers · CPC title

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title

• H10D30/6219

  characterised by the source or drain electrodes · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title