Semiconductor structure and method for manufacturing memory

Patent metadata

Field	Value
Publication number	US-12598732-B2
Application number	US-202217935033-A
Country	US
Kind code	B2
Filing date	Sep 23, 2022
Priority date	May 30, 2022
Publication date	Apr 7, 2026
Grant date	Apr 7, 2026

Abstract

A semiconductor structure includes a plurality memory group provided in rows, each of the memory groups includes a plurality of memories arranged at intervals along a row direction, and for two adjacent ones of the memory groups, the memories in one memory group and the memories in another memory group are staggered.

First claim

What is claimed is:

1 . A semiconductor structure comprising a plurality of memory groups provided in rows, each of the memory groups comprising a plurality of memories arranged at intervals along a row direction, wherein for two adjacent ones of the memory groups, the memories in one memory group and the memories in another memory group are staggered;
wherein each of the memories comprises two memory cell arrays and a bit line structure, and the two memory cell arrays are located at opposite sides of the bit line structure in the row direction; and wherein the bit line structure extends along a first direction and is electrically connected with transistors in the two memory cell arrays, one end of the bit line structure protrudes from the memory cell arrays and has step surfaces, and the protruding part of the bit line structure is located between adjacent memories in a memory group adjacent to the protruding part; and wherein the first direction and the row direction are perpendicular to each other and are located in a same horizontal plane.

2 . The semiconductor structure according to claim 1 , wherein each of the memory groups comprises a first sub-memory group and a second sub-memory group, the first sub-memory group and the second sub-memory group are arranged at intervals along the first direction, and the first sub-memory group and the second sub-memory group are arranged symmetrically with respect to the row direction.

3 . The semiconductor structure according to claim 1 , wherein a memory cell array comprises a plurality of memory cell layers, the plurality of memory cell layers are arranged at intervals along a second direction, for two adjacent ones of the memory cell layers, a projection of one memory cell layer on an other memory cell layer coincides with the other memory cell layer; and wherein the second direction, the first direction and the row direction are perpendicular to each other; and
wherein each of the memory cell layers comprises a plurality of memory cells arranged at intervals along the first direction, and each of the memory cells comprises a transistor and a capacitor connected to the transistor.

4 . The semiconductor structure according to claim 2 , wherein a memory cell array comprises a plurality of memory cell layers, the plurality of memory cell layers are arranged at intervals along a second direction, for two adjacent ones of the memory cell layers, a projection of one memory cell layer on an other memory cell layer coincides with the other memory cell layer; and wherein the second direction, the first direction and the row direction are perpendicular to each other; and
wherein each of the memory cell layers comprises a plurality of memory cells arranged at intervals along the first direction, and each of the memory cells comprises a transistor and a capacitor connected to the transistor.

5 . The semiconductor structure according to claim 3 , wherein each of the memory cells has a plurality of capacitors, the plurality of capacitors are arranged at intervals along the row direction, and the plurality of the capacitors are connected to each other by one electrode layer.

6 . The semiconductor structure according to claim 5 , wherein the bit line structure comprises a plurality of bit lines arranged at intervals along the second direction, each of the bit lines is connected with the transistors of all the memory cells in a memory cell layer located at a same layer, and an end of the transistor connected to a bit line is different from an end of the transistor connected to the capacitor.

7 . The semiconductor structure according to claim 6 , wherein each of the bit lines other than an uppermost bit line comprises a first segment and a second segment connected in sequence, and a width of the second segment is shorter than a width of the first segment; and
wherein at least part of the second segment is located between adjacent memories in the memory group adjacent to the second segment.

8 . The semiconductor structure according to claim 7 , wherein a memory further comprises a word line structure comprising a plurality of word lines arranged at intervals along the first direction, and each of the word lines extends along the second direction.

9 . The semiconductor structure according to claim 8 , further comprising first data lines, second data lines and a third data line;
wherein the first data lines are connected with the bit line structure; and wherein a second data line is connected to a word line, and the third data line is connected to the capacitor of the memory.

10 . A method for manufacturing a memory in the semiconductor structure according to claim 1 , comprising:
providing a substrate having a first region, a second region and a third region, the first region and the third region being symmetrically arranged at two sides of the second region; forming the two memory cell arrays in the first region and the third region, respectively; and forming the bit line structure in the second region, and the bit line structure being electrically connected with the transistors in the two memory cell arrays; wherein the one end of the bit line structure protrudes from the memory cell arrays and has the step surfaces.

11 . The method according to claim 10 , wherein the first region comprises a first sub-region and a second sub-region connected to each other, the first sub-region is used for forming a transistor and the second sub-region is used for forming a capacitor;
wherein the forming the two memory cell arrays in the first region and the third region, respectively comprises: forming columns of stacked structures arranged at intervals along the first direction in the first region and the third region, and a first trench being formed between two adjacent ones of the columns of the stacked structures; and forming a laminated structure in the second region; wherein each of the columns of the stacked structures comprises a plurality of sacrificial layers and a plurality of active layers alternately stacked, and film layers of the laminated structure are same as film layers of a stacked structure; forming a second dielectric layer in first trenches, the second dielectric layer extending outside the first trenches and covering top surfaces of the columns of the stacked structures; removing part of a sacrificial layer located at the first region and the third region to form a second trench in communication with the first trench; forming a support structure in the first trenches and second trenches to support any adjacent active layers; removing a remaining sacrificial layer and forming a first dielectric layer in a region where the remaining sacrificial layer is located; removing part of the first dielectric layer and part of the second dielectric layer in the first sub-region to form a filling region, the filling region exposing part of an active layer, and the exposed part being used for forming a channel region of the transistor; forming a gate oxide layer and word lines in the filling region, wherein the word lines and the gate oxide layer surrounding the active layers together with the active layers constitute the transistor; and forming the capacitor being connected with the transistor in the second sub-region.

12 . The method according to claim 11 , wherein the capacitor comprises a first electrode layer, a dielectric layer and a second electrode layer; and the first electrode layer, the dielectric layer and the second electrode layer sequentially surrounds the active layers in the second sub-region.

13 . The method according to claim 11 , wherein after forming the capacitor being conne

Assignees

• Changxin Memory Tech Inc

Inventors

• Jiang Yi
• Xiao Deyuan
• Su Xingsong
• Liu Youming

Classifications

• H10B12/482

  Bit lines · CPC title

• H10B12/05 Primary

  Making the transistor · CPC title

• H10B12/03

  Making the capacitor or connections thereto · CPC title

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• H10D89/10

  Integrated device layouts · CPC title