Methods and systems for updating device firmware while maintaining state and connectivity

Patent metadata

Field	Value
Publication number	US-12596546-B2
Application number	US-202418674310-A
Country	US
Kind code	B2
Filing date	May 24, 2024
Priority date	Jul 8, 2022
Publication date	Apr 7, 2026
Grant date	Apr 7, 2026

Abstract

A system and related method, including a first processor core, a second processor core and a control circuitry to receive requests to update existing firmware of the first processor core to a new firmware. The control circuitry loads existing firmware onto the second processor core and migrates data associated with the existing firmware on the first processor core to the second processor core. The control circuitry stops the transaction execution by the first processor core while causing the second processor core to execute transactions in place of the first processor core. The control circuitry restarts the first processor core, replaces the existing firmware on the first processor core with the new firmware, and migrates data of the existing firmware on the second processor core to the first processor core. The control circuitry stops the transaction execution of the second processor core and causes the first processor core to execute transactions.

First claim

What is claimed is:

1 . A method for modifying a processor core of a plurality of processor cores, the method comprising:
identifying a first software executing on a first processor core of the plurality of processor cores; loading the first software on a second processor core of the plurality of processor cores; migrating first data associated with an operating state of the first software on the first processor core to the second processor core; causing the first processor core to stop executing the first software; causing the second processor core to execute the first software based on the first data; loading a second software on the first processor core; migrating second data associated with an operating state of the first software on the second processor core to the first processor core; and causing the first processor core to execute the second software based on the second data.

2 . The method of claim 1 , wherein the first processor core and the second processor core are coupled to a peripheral component interconnect express (PCIe) interface.

3 . The method of claim 1 , wherein the first processor core and the second processor core are coupled to an ethernet interface.

4 . The method of claim 1 , further comprising determining that the second processor core is available.

5 . The method of claim 1 , wherein migrating first data associated with the operating state of the first software on the first processor core to the second processor core comprises loading the first data associated with the operating state of the first software on the first processor core onto an available area of memory associated with the second processor core.

6 . The method of claim 1 , wherein the first data associated with the operating state of the first software on the first processor core and the second data associated with the operating state of the first software on the second processor core respectively comprise:
a plurality of outstanding transactions; a state of the first software; and an input/output connectivity state of the first software.

7 . The method of claim 1 , further comprising restarting the first processor core, wherein the restarting the first processor core occurs after the second processor core begins to execute the first software based on the first data and before loading the second software on the first processor core.

8 . A system comprising:
a plurality of processor cores; and control circuitry, wherein the control circuitry is communicatively coupled to the plurality of processor cores, the control circuitry configured to:
identify a first software executing on a first processor core of the plurality of processor cores;
load the first software on a second processor core of the plurality of processor cores;
migrate first data associated with an operating state of the first software on the first processor core to the second processor core;
cause the first processor core to stop executing the first software;
cause the second processor core to execute the first software based on the first data;
load a second software on the first processor core;
migrate second data associated with an operating state of the first software on the second processor core to the first processor core; and
cause the first processor core to execute the second software based on the second data.

9 . The system of claim 8 , wherein the first processor core and the second processor core are coupled to a peripheral component interconnect express (PCIe) interface.

10 . The system of claim 8 , wherein the first processor core and second processor core are coupled to an ethernet interface.

11 . The system of claim 8 , wherein the control circuitry is further to determine that the second processor core is available.

12 . The system of claim 8 , wherein the control circuitry is to load the first data associated with the operating state of the first software on the first processor core onto an available area of memory associated with the second processor core.

13 . The system of claim 8 , wherein the first data associated with the operating state of the first software on the first processor core and the second data associated with the operating state of the first software on the second processor core respectively comprise:
a plurality of outstanding transactions; a state of the first software; and an input/output connectivity state of the first software.

14 . The system of claim 8 , wherein the control circuitry is further to restart the first processor core after the second processor core begins to execute the first software based on the first data and before loading the second software on the first processor core.

15 . A solid state drive (SSD) device comprising:
a plurality of processor cores; and a controller, wherein the controller is communicatively coupled to the plurality of processor cores, the controller configured to:
identify a first software executing on a first processor core of the plurality of processor cores;
load the first software on a second processor core of the plurality of processor cores;
migrate first data associated with an operating state of the first software on the first processor core to the second processor core;
cause the first processor core to stop executing the first software;
cause the second processor core to execute the first software based on the first data;
load a second software on the first processor core;
migrate second data associated with an operating state of the first software on the second processor core to the first processor core; and
cause the first processor core to execute the second software based on the second data.

16 . The SSD device of claim 15 , wherein the first processor core and the second processor core are coupled to a peripheral component interconnect express (PCIe) interface.

17 . The SSD device of claim 15 , wherein the first processor core and second processor core are coupled to an ethernet interface.

18 . The SSD device of claim 15 , wherein the controller is further to determine that the second processor core is available.

19 . The SSD device of claim 15 , wherein the controller is to load the first data associated with the operating state of the first software on the first processor core onto an available area of memory associated with the second processor core.

20 . The SSD device of claim 15 , wherein the first data associated with the operating state of the first software on the first processor core and the second data associated with the operating state of the first software on the second processor core respectively comprise:
a plurality of outstanding transactions; a state of the first software; and an input/output connectivity state of the first software.

21 . The SSD device of claim 15 , wherein the controller is further to restart the first processor core after the second processor core begins to execute the first software based on the first data and before loading the second software on the first processor core.

Assignees

• Sk Hynix Nand Product Solutions Corp

Inventors

• Hallett Timothy
• Khambam Bindu Madhavi
• Rajagopalan Kailaash
• Govindane Mahesh
• Fitzpatrick Matthew
• Povilus Sam
• Nolan John
• Hughes Jonathan M

Classifications

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F11/2284

  by power-on test, e.g. power-on self test [POST] · CPC title

• G06F9/44505

  Configuring for program initiating, e.g. using registry, configuration files · CPC title

• G06F11/1435

  using file system or storage system metadata · CPC title

• G06F9/505

  considering the load · CPC title