Replacing an accelerator firmware image without operating system reboot

Patent metadata

Field	Value
Publication number	US-2017123780-A1
Application number	US-201614987074-A
Country	US
Kind code	A1
Filing date	Jan 4, 2016
Priority date	Oct 28, 2015
Publication date	May 4, 2017
Grant date	—

Abstract

The present disclosure relates to updating a firmware image on a coherent hardware accelerator concurrently with executing operations on the coherent hardware accelerator. According to one embodiment, while executing accelerator-enabled operations on the coherent hardware accelerator, a system stores a firmware update package in a local memory on the coherent hardware accelerator. Once the firmware update package is stored in local memory on the coherent hardware accelerator, the system restarting the coherent hardware accelerator by pausing the execution of at least a first operation initiated on the coherent hardware accelerator and applying the firmware update package to the firmware image on the coherent hardware accelerator. Once the firmware update package is applied to the coherent hardware accelerator, the system resumes the operation on the coherent hardware accelerator.

First claim

What is claimed is:

1 . A method for updating a firmware image on a coherent hardware accelerator concurrently with executing operations on the coherent hardware accelerator, comprising:
while executing accelerator-enabled operations on the coherent hardware accelerator, storing a firmware update package in a local memory on the coherent hardware accelerator; restarting the coherent hardware accelerator by:
pausing the execution of at least a first operation initiated on the coherent hardware accelerator, and
applying the firmware update package to the firmware image on the coherent hardware accelerator; and
resuming the operation on the coherent hardware accelerator.

2 . The method of claim 1 , wherein the accelerator-enabled operation comprises input/output (I/O) operations or instruction execution using one or more virtual memory addresses of the system memory.

3 . The method of claim 1 , wherein pausing an operation executing on the coherent hardware accelerator comprises saving at least one of:
one or more interrupt source numbers identifying the paused operation; a range of memory mapped input/output (I/O) (MMIO) addresses associated with the paused operation; a program counter associated with an instruction most recently executed by the paused operation; or a most recently executed I/O command associated with the paused operation.

4 . The method of claim 3 , wherein resuming the operation comprises restoring at least one of the one or more interrupt source numbers, the range of MMIO addresses associated with the operation, the program counter associated with an instruction most recently executed by the operation, or the most recently executed I/O command associated with the operation.

5 . The method of claim 1 , further comprising:
after pausing an operation executing on the coherent hardware accelerator, resuming the operation using a software algorithm executing on a processor other than the hardware accelerator.

6 . The method of claim 1 , wherein the operations executing on the coherent hardware accelerator are paused in response to detecting a timeout condition relative to an expected response time from the coherent hardware accelerator when an operation attempts to transmit a command to the coherent hardware accelerator.

7 . The method of claim 1 , wherein the operations executing on the coherent hardware accelerator are paused in response to detecting a reserved value when the operations query the hardware accelerator for a state of the hardware accelerator.

8 . The method of claim 1 , further comprising:
while resuming the operation on the coherent hardware accelerator, querying a configuration of the updated coherent hardware accelerator and making the configuration available to an operating system for discovery and use in subsequent operations.

Assignees

• IBM

Inventors

• Albot Andre L
• Aslot Vishal C
• Burks Iii Thomas V
• Dietel John D

Classifications

• G06F2213/2424

  Interrupt packet, e.g. event · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F8/654

  using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories · CPC title

• G06F8/65 Primary

  Updates (security arrangements therefor G06F21/57) · CPC title

• G06F13/24

  using interrupt (G06F13/32 takes precedence) · CPC title