Memory system and power supply control circuit

Patent metadata

Field	Value
Publication number	US-12596489-B2
Application number	US-202418433682-A
Country	US
Kind code	B2
Filing date	Feb 6, 2024
Priority date	Feb 16, 2023
Publication date	Apr 7, 2026
Grant date	Apr 7, 2026

Abstract

A memory system includes a memory controller, a non-volatile memory, and a power supply control circuit configured to receive power from an external power supply. The power supply control circuit includes a backup power supply, a first converter configured to supply power to the memory controller based on power supplied from the external power supply or the backup power supply, a second converter configured to supply power to the non-volatile memory based on power supplied from the external power supply or the backup power supply, and a discharge circuit configured to discharge the power remaining in the second converter based on power remaining in the backup power supply after the supply of power from the external power supply and the backup power supply is stopped.

First claim

What is claimed is:

1 . A memory system comprising:
a memory controller; a non-volatile memory; and a power supply control circuit configured to receive power from an external power supply, wherein the power supply control circuit includes:
a backup power supply;
a first converter configured to supply power to the memory controller based on power supplied from the external power supply or the backup power supply;
a second converter configured to supply power to the non-volatile memory based on power supplied from the external power supply or the backup power supply, and
a discharge circuit configured to discharge power remaining in the second converter based on power remaining in the backup power supply, after the supply of power from the external power supply and the backup power supply is stopped, wherein the discharge circuit includes:
a first resistor having a first end connected to the backup power supply;
a first transistor connected in series to the first resistor;
a second resistor having a first end connected between the first converter and the non-volatile memory; and
a second transistor connected in series to the second resistor, the second transistor having a control end connected between the first resistor and the first transistor.

2 . The memory system according to claim 1 ,
wherein a resistance value of the first resistor is 10 kΩor more and 100 kΩ or less.

3 . The memory system according to claim 1 ,
wherein a resistance value of the second resistor is 100 Ω or more and 1 kΩ or less.

4 . The memory system according to claim 1 ,
wherein the discharge circuit is configured to discharge the power remaining in the first converter based on the power remaining in the backup power supply, after the supply of power from the external power supply and the backup power supply is stopped.

5 . The memory system according to claim 4 ,
wherein the discharge circuit includes:
a first resistor having a first end connected to the backup power supply;
a first transistor connected in series to the first resistor;
a second resistor having a first end connected between the first converter and the non-volatile memory;
a second transistor connected in series to the second resistor, the second transistor having a control end connected between the first resistor and the first transistor;
a third resistor having a first end connected between the second converter and the memory controller; and
a third transistor connected in series to the third resistor, the third transistor having a control end connected between the first resistor and the first transistor.

6 . The memory system according to claim 1 , further comprising:
a control circuit configured to supply power to the first converter and the second converter based on power supplied from the external power supply or the backup power supply, wherein the discharge circuit is configured to discharge the power remaining in the control circuit based on the power remaining in the backup power supply, after the supply of power from the external power supply and the backup power supply is stopped.

7 . The memory system according to claim 6 ,
wherein the discharge circuit includes:
a first resistor having a first end connected to the backup power supply;
a first transistor connected in series to the first resistor;
a second resistor having a first end connected between the first converter and the non-volatile memory;
a second transistor connected in series to the second resistor, the second transistor having a control end connected between the first resistor and the first transistor;
a fourth resistor having a first end connected between the control circuit and the first converter and the second converter; and
a fourth transistor connected in series to the fourth resistor, the fourth transistor having a control end connected between the first resistor and the first transistor.

8 . A power supply control circuit comprising:
a backup power supply; a converter configured to supply power externally based on power supplied from an external power supply or the backup power supply; and a discharge circuit configured to discharge power remaining in the converter based on power remaining in the backup power supply, after the supply of power from the external power supply and the backup power supply is stopped, wherein the discharge circuit includes:
a first resistor having a first end connected to the backup power supply;
a first transistor connected in series to the first resistor;
a second resistor having a first end connected between the converter and a non-volatile memory; and
a second transistor connected in series to the second resistor and having a control end connected between the first resistor and the first transistor.

9 . The power supply control circuit according to claim 8 , further comprising:
a control circuit configured to supply power to the converter based on power supplied from the main power supply or the backup power supply; wherein the discharge circuit is configured to discharge power remaining in the control circuit based on the power remaining in the backup power supply, after the supply of power from the main power supply and the backup power supply is stopped.

10 . The power supply control circuit according to claim 9 , wherein the discharge circuit further includes:
a third resistor having a first end connected between the control circuit and the converter; and a third transistor connected in series to the fourth resistor, the fourth transistor having a control end connected between the first resistor and the first transistor.

11 . The memory system according to claim 1 , wherein the first transistor includes an N-type transistor.

Assignees

• Kioxia Corp

Inventors

• Hibe Yuta
• Kamada Daiki
• Kumagai Kengo

Classifications

• G06F3/0658

  Controller construction arrangements · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0625 Primary

  Power saving in storage systems · CPC title