Power supply device and power supply method using the same

Patent metadata

Field	Value
Publication number	US-9819223-B2
Application number	US-201414509755-A
Country	US
Kind code	B2
Filing date	Oct 8, 2014
Priority date	Nov 11, 2013
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

A power supply for supplying power to a chipset includes a first voltage regulating circuit, which is configured to convert an applied power supply signal into a group of first supply voltages, and a second voltage regulating circuit, which is configured to convert the applied power supply signal into a group of second supply voltages. A control circuit is provided, which is configured to selectively enable the second voltage regulating circuit to generate the group of second supply voltages. An output discharge circuit is provided, which is configured to discharge an output stage of the first voltage regulating circuit in response to a transition of the first voltage regulating circuit from an active state to an inactive state. This transition of the first voltage regulating circuit from an active state to an inactive state can occur in response to a change in magnitude of the power supply signal.

First claim

What is claimed is:

1. An integrated circuit power supply, comprising:
a first voltage regulating circuit configured to convert an applied power supply signal into a group of first supply voltages provided to an output of the power supply;
a second voltage regulating circuit configured to convert the applied power supply signal into a group of second supply voltages provided to the output of the power supply;
a control circuit configured to selectively enable the second voltage regulating circuit to generate the group of second supply voltages;
an output discharge circuit configured to discharge an output stage of the first voltage regulating circuit in response to a transition of the first voltage regulating circuit from an active state to an inactive state; and
a sequence control circuit configured to generate an enable signal in response to a change in magnitude of the power supply signal,
wherein the first voltage regulating circuit generates the group of first supply voltages in response to the enable signal.

2. The power supply of claim 1 , wherein the transition of the first voltage regulating circuit from an active state to an inactive state occurs in response to a change in magnitude of the power supply signal.

3. The power supply of claim 2 , further comprising an input discharge circuit configured to discharge an input stage of the first voltage regulating circuit in response to the transition of the first voltage regulating circuit from an active state to an inactive state.

4. The power supply of claim 1 , further comprising a backup power supply circuit configured to store energy derived from the applied power supply signal and provide the stored energy as power to the output discharge circuit.

5. A power supply device for supplying power to a chipset of a semiconductor device comprising:
a pre-control voltage regulate unit configured to convert main power into a pre-control supply voltage group including at least one pre-control supply voltage and to provide the pre-control supply voltage group to the chipset in response to the main power;
a post-control voltage regulate unit configured to convert the main power into a post-control supply voltage group including at least one post-control supply voltage and to provide the post-control supply voltage group to the chipset in response to the main power;
a control unit configured to provide a command which activates the post-control supply voltage group to the chipset so that the chipset uses the post-control voltage supply group; and
an output discharge unit configured to discharge remaining charges at an output stage of the pre-control voltage regulate unit when the pre-control voltage regulate unit is in an inactivate state in response to a level of the main power.

6. The power supply device of claim 5 , further comprising a sequence control unit configured to receive the main power to generate an enable signal,
wherein the pre-control voltage regulate unit provides the pre-control supply voltage group to the chipset in response to the enable signal.

7. The power supply device of claim 6 , wherein the sequence control unit comprises:
a voltage detect unit configured to output a signal when a voltage level of the main power reaches a pre-designated level; and
a delay unit configured to delay the output signal output from the voltage detect unit,
wherein the voltage detect unit comprises:
a first voltage detector configured to output a first signal when a voltage level of the main power reaches a first detecting level; and
a second voltage detector configured to output a second signal when a voltage level of the main power reaches a second detecting level,
wherein the delay unit comprises:
a first delayer connected to the first voltage detector to delay the first signal for a first delay time; and
a second delayer connected to the second voltage detector to delay the second signal for a second delay time, and
wherein the delayed first signal is output as a first enable signal and the delayed second signal is output as a second enable signal.

8. The power supply device of claim 7 , wherein the first delayer outputs a low level signal without delay of the first signal if the first signal has a low level, and
wherein the second delayer outputs a low level signal without delay of the second signal if the second signal has a low level.

9. The power supply device of claim 7 , wherein the pre-control voltage regulate unit comprises:
a first voltage regulator configured to convert the main power into a first supply voltage according to the first enable signal; and
a second voltage regulator configured to convert the main power into a second supply voltage according to the second enable signal,
wherein an enforced discharge unit comprises:
a first enforced discharger configured to discharge remaining charges in the first voltage regulator according to the first inverting signal; and
a second enforced discharger configured to discharge remaining charges in the second voltage regulator according to the second inverting signal, and
wherein the first inverting signal is an inverted signal of the first enable signal and the second inverting signal is an inverted signal of the second enable signal.

10. The power supply device of claim 6 , further comprising a discharge control unit configured to receive the enable signal to generate a discharge signal indicating an operation state of the pre-control voltage regulate unit,
wherein the output discharge unit discharges remaining charges at an output stage of the pre-control voltage regulate unit according to the discharge signal when the pre-control voltage regulate unit is in an inactivated state.

11. The power supply device of claim 6 , further comprising an input discharge unit configured to discharge remaining charges at an input stage of the pre-control voltage regulate unit according to the discharge signal when the pre-control voltage regulate unit is in an inactivated state.

12. The power supply device of claim 10 , further comprising a backup power unit configured to store power from the main power and to provide the stored power to the discharge control unit and the output discharge unit.

13. The power supply device of claim 5 , wherein the control unit generates a reset signal for resetting the chipset, provides the reset signal to the chipset, and then provides the command to the chipset.

14. The power supply device of claim 13 , further comprising a memory configured to load firmware booting the semiconductor device,
wherein the control unit executes firmware loaded in the memory and provides the command to the chipset in the process of booting.

15. The power supply device of claim 5 , wherein the output discharge unit comprises:
a load connected to the pre-control voltage control unit; and
a switch connected to the load to turn on-off according the discharge signal,
wherein the quantity of discharge currents is variable according to a size of the load.

16. The power supply device of claim 5 , wherein the command is provided as a form of a set feature command.

17. A method for supplying power to a chipset of a semiconductor device comprising:
applying a main power to a power supply device;
converting the main power into at least one pre-control supply voltage and at least one post-control supply voltage and providing the at least one post-control supply voltage to the chipset;
discharging remaining charges of the power supply device for a pre-designated delay time;
providing the at least one pre-control supply voltage to th

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jeon Sang Hun
• Chun Ho-Jin

Classifications

• H02J9/061 Primary

  for DC powered loads · CPC title

• H02M3/1584

  with a plurality of power processing stages connected in parallel · CPC title

• H02J7/007

  Electricity · mapped topic

• G11C5/147

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• H02H7/1222

  responsive to abnormalities in the input circuit, e.g. transients in the DC input · CPC title