Integrated passive devices (IPD) having a baseband damping resistor for radiofrequency power devices and devices and processes implementing the same

Patent metadata

Field	Value
Publication number	US-12593697-B2
Application number	US-202218145961-A
Country	US
Kind code	B2
Filing date	Dec 23, 2022
Priority date	Dec 23, 2022
Publication date	Mar 31, 2026
Grant date	Mar 31, 2026

Abstract

A transistor device includes a metal submount; a transistor die arranged on said metal submount; an IPD component arranged on said metal submount, and the IPD component having a baseband damping resistor arranged on a thermally conductive dielectric substrate; and a second IPD component arranged on said metal submount, and the second IPD component may include a baseband decoupling capacitor arranged on a thermally conductive dielectric substrate.

First claim

What is claimed is:

1 . A transistor device, comprising:
a metal submount; a transistor die arranged on said metal submount; an IPD component arranged on said metal submount, the IPD component comprising a baseband damping resistor arranged on a thermally conductive dielectric substrate; and a second IPD component arranged on said metal submount, the second IPD component comprises a baseband decoupling capacitor arranged on a second thermally conductive dielectric substrate.

2 . The transistor device according to claim 1 wherein the thermally conductive dielectric substrate of the IPD component comprises silicon carbide (SiC).

3 . The transistor device according to claim 1 wherein the second thermally conductive dielectric substrate of the second IPD component comprises silicon carbide (SIC).

4 . The transistor device according to claim 1 wherein the IPD component comprises a first IPD component configured as an output capacitor IPD; and wherein the thermally conductive dielectric substrate of the first IPD component is attached to the metal submount via a die attach material.

5 . The transistor device according to claim 4 wherein the output capacitor IPD comprises a DC blocking capacitor; and wherein the DC blocking capacitor comprises a lower capacitor metal, a capacitor dielectric material, and an upper capacitor metal on an upper surface of the second thermally conductive dielectric substrate.

6 . The transistor device according to claim 4 wherein the thermally conductive dielectric substrate of the output capacitor IPD is attached to the metal submount via a die attach material; and wherein the metal submount comprises a support, a surface, a package support, a package surface, a package support surface, a flange, a metal flange, a heat sink, a common source support, a common source surface, a common source package support, a common source package surface, a common source package support surface, a common source flange, a common source heat sink, a leadframe, and/or a metal leadframe.

7 . The transistor device according to claim 1 wherein the second thermally conductive dielectric substrate of the second IPD component is attached to the metal submount via a die attach material; and wherein the metal submount comprises a support, a surface, a package support, a package surface, a package support surface, a flange, a metal flange, a heat sink, a common source support, a common source surface, a common source package support, a common source package surface, a common source package support surface, a common source flange, a common source heat sink, a leadframe, and/or a metal leadframe.

8 . The transistor device according to claim 1 wherein the baseband damping resistor is implemented as a thin film resistor and/or a bulk resistor arranged on an upper surface of the thermally conductive dielectric substrate; and wherein the thermally conductive dielectric substrate of the IPD component is attached to the metal submount via a die attach material.

9 . The transistor device according to claim 1 further comprising a first IPD component configured as an output capacitor IPD,
wherein the IPD component comprises a third IPD component.

10 . The transistor device according to claim 9 wherein the first IPD component comprises a silicon carbide (SiC) substrate; and wherein the transistor die, the IPD component, and the second IPD component are attached to said metal submount via a die attach material.

11 . The transistor device according to claim 1 further comprising a fourth IPD component,
wherein the fourth IPD component comprises a resistor and/or a capacitor.

12 . The transistor device according to claim 11 further comprising an input network, wherein the fourth IPD component is connected to the input network.

13 . The transistor device according to claim 1 wherein the transistor die comprises one or multiple LDMOS transistor die.

14 . The transistor device according to claim 1 wherein the transistor die comprises one or multiple GaN based HEMTs.

15 . The transistor device according to claim 1 wherein the transistor device comprises a plurality of the transistor die.

16 . The transistor device according to claim 15 wherein the plurality of the transistor die are configured in a Doherty configuration.

17 . A process for implementing a transistor device, comprising,
providing a metal submount; arranging a transistor die on said metal submount; arranging an IPD component comprising a baseband damping resistor arranged on a thermally conductive dielectric substrate; and arranging a second IPD component that comprises a baseband decoupling capacitor arranged on a second thermally conductive dielectric substrate.

18 . The process for implementing a transistor device according to claim 17 wherein the thermally conductive dielectric substrate of the IPD component comprises silicon carbide (SiC).

19 . The process for implementing a transistor device according to claim 17 wherein the second thermally conductive dielectric substrate of the second IPD component comprises silicon carbide (SiC).

20 . The process for implementing a transistor device according to claim 17 wherein the IPD component comprises a first IPD component configured as an output capacitor IPD; and wherein the thermally conductive dielectric substrate of the first IPD component is attached to the metal submount via a die attach material.

21 . The process for implementing a transistor device according to claim 20 wherein the output capacitor IPD comprises a DC blocking capacitor; and wherein the DC blocking capacitor comprises a lower capacitor metal, a capacitor dielectric material, and an upper capacitor metal on an upper surface of the second thermally conductive dielectric substrate.

22 . The process for implementing a transistor device according to claim 20 wherein the thermally conductive dielectric substrate of the output capacitor IPD is attached to the metal submount via a die attach material; and wherein the metal submount comprises a support, a surface, a package support, a package surface, a package support surface, a flange, a metal flange, a heat sink, a common source support, a common source surface, a common source package support, a common source package surface, a common source package support surface, a common source flange, a common source heat sink, a leadframe, and/or a metal leadframe.

23 . The process for implementing a transistor device according to claim 17 wherein the second thermally conductive dielectric substrate of the second IPD component is attached to the metal submount via a die attach material; and wherein the metal submount comprises a support, a surface, a package support, a package surface, a package support surface, a flange, a metal flange, a heat sink, a common source support, a common source surface, a common source package support, a common source package surface, a common source package support surface, a common source flange, a common source heat sink, a leadframe, and/or a metal leadframe.

24 . The process for implementing a transistor device according to claim 17 wherein the baseband damping resistor is implemented as a thin film resistor and/or a bulk resistor arranged on an upper surface of the thermally conductive dielectric substrate; and wherein the thermally conductive dielectric substrate of the IPD component is

Assignees

• Macom Tech Solutions Holdings Inc
• Wolfspeed Inc

Inventors

• Jang Haedong
• Hasan Mehdi
• Marbell Marvin
• Fisher Jeremy

Classifications

• H10W72/50

  Bond wires · CPC title

• H10W90/755

  between a chip and a laterally-adjacent insulating package substrate, interpose or RDL · CPC title

• H10W44/241

  for passive devices or passive elements · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W76/15 Primary

  Containers comprising an insulating or insulated base · CPC title