Apparatuses and memory devices including air gaps between conductive lines

Patent metadata

Field	Value
Publication number	US-12593679-B2
Application number	US-202217818317-A
Country	US
Kind code	B2
Filing date	Aug 8, 2022
Priority date	Aug 11, 2020
Publication date	Mar 31, 2026
Grant date	Mar 31, 2026

Abstract

A method of forming an apparatus includes forming pillar structures extending vertically through a first isolation material, forming conductive lines operatively coupled to the pillar structures, forming dielectric structures overlying the conductive lines, and forming air gaps between neighboring conductive lines. The air gaps are laterally adjacent to the conductive lines with a portion of the air gaps extending above a plane of an upper surface of the laterally adjacent conductive lines and a portion of the air gaps extending below a plane of a lower surface of the laterally adjacent conductive lines. Apparatuses, memory devices, methods of forming a memory device, and electronic systems are also disclosed.

First claim

What is claimed is:

1 . An apparatus, comprising:
pillars extending vertically through an isolation material; conductive lines overlying the pillars; dielectric structures overlying the conductive lines; air gaps separating laterally neighboring conductive lines from one another, an upper portion of the air gaps laterally adjacent to the dielectric structures and a lower portion of the air gaps laterally adjacent to the isolation material, at least portions of the air gaps located immediately adjacent to the conductive lines, and portions of the isolation material substantially surrounding the air gaps on at least two consecutive sides, first portions of the isolation material laterally adjacent to the lower portion of the air gaps, and second portions of the isolation material vertically adjacent to the air gaps; interconnect structures underlying the conductive lines; and contact structures underlying the interconnect structures and overlying the pillars, the air gaps separated from the interconnect structures on at least one side by the first portions of the isolation material, and the air gaps separated from the contact structures by the second portions of the isolation material.

2 . The apparatus of claim 1 , wherein the dielectric structures comprise elongated portions of a hard mask material directly on the conductive lines, opposing sidewalls of the hard mask material vertically aligned with opposing sidewalls of the conductive lines.

3 . The apparatus of claim 1 , wherein the pillars comprise a channel material substantially surrounding an insulative material, the air gaps vertically aligned with the channel material and the insulative material of the pillars.

4 . The apparatus of claim 1 , further comprising an additional isolation material overlying the dielectric structures and the air gaps, wherein the air gaps are defined by the additional isolation material, the dielectric structures, the conductive lines, and the isolation material.

5 . The apparatus of claim 4 , wherein portions of the additional isolation material are vertically adjacent to the isolation material and additional portions of the additional isolation material are laterally adjacent to the isolation material, a material composition of the additional isolation material differing from a material composition of the isolation material.

6 . An apparatus, comprising:
strings of memory cells extending vertically through an alternating sequence of conductive structures and insulative structures arranged in tiers, the strings of memory cells comprising oxide-nitride-oxide (ONO) structures substantially surrounding a channel; data lines overlying the strings of memory cells; and air gaps intervening between laterally neighboring data lines, the air gaps within horizontal boundaries of the ONO structures and the data lines external to the horizontal boundaries of the ONO structures, a portion of the air gaps extending beyond an upper surface of the data lines and another portion of the air gaps extending beyond a lower surface of the data lines, the air gaps exhibiting a width that is relatively greater than a width of the data lines in a horizontal direction that is substantially orthogonal to another horizontal direction in which the data lines extend.

7 . The apparatus of claim 6 , further comprising an insulative material overlying the strings of memory cells, upper portions of the insulative material configured as L-shaped structures adjacent to the air gaps.

8 . The apparatus of claim 6 , wherein the air gaps are centrally located between the laterally neighboring data lines with the portion of the air gaps extending beyond the upper surface of the data lines exhibiting a height substantially equal to a height of the other portion of the air gaps extending beyond the lower surface of the data lines.

9 . The apparatus of claim 6 , wherein the width of the air gaps is between about 20 nm and about 100 nm, and the width of the data lines is between about 10 nm and about 60 nm.

10 . The apparatus of claim 6 , wherein regions between laterally neighboring data lines are substantially free of insulative material.

11 . A memory device, comprising:
pillar structures extending vertically through one or more insulative materials; conductive lines overlying the pillar structures and extending in a first horizontal direction; insulative structures overlying the conductive lines; air gaps between laterally neighboring conductive lines, the conductive lines exhibiting a width that is substantially equal to a width of the insulative structures in a second horizontal direction orthogonal to the first horizontal direction, and the air gaps exhibiting a height in a vertical direction that is relatively greater than a combined height of the conductive lines and the insulative structures in the vertical direction; and a first dielectric material and a second dielectric material adjacent to the air gaps, the first dielectric material contacting vertical and horizontal surfaces of each insulative structure and defining upper boundaries of the air gaps, and the second dielectric material contacting the conductive lines and defining lower boundaries of the air gaps.

12 . The memory device of claim 11 , wherein the air gaps extend below lower surfaces of the conductive lines.

13 . The memory device of claim 11 , wherein the conductive lines and insulative structures comprise subtractive patterned features with a critical dimension of the conductive lines being relatively less than a critical dimension of the air gaps.

14 . The memory device of claim 11 , wherein central portions of the air gaps are located immediately adjacent to the conductive lines along a height of the conductive lines.

15 . The memory device of claim 11 , further comprising one or more conductive contacts between the pillar structures and conductive lines, the one or more conductive contacts comprising tungsten and the conductive lines comprising a single material comprising ruthenium, molybdenum, or tungsten nitride.

16 . The memory device of claim 15 , wherein the insulative structures and the conductive lines are self-aligned with an uppermost conductive contact underlying the conductive lines, at least one outer side surface of each of the insulative structures and the conductive lines vertically aligned with an outer side surface of the uppermost conductive contact.

Assignees

• Micron Technology Inc

Inventors

• Gupta Sidhartha
• Economy David Ross
• Hill Richard J
• Ritter Kyle A
• Kaushik Naveen

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/48

  Insulating materials thereof · CPC title