Dual contact process with selective deposition

Patent metadata

Field	Value
Publication number	US-12593486-B2
Application number	US-202017033373-A
Country	US
Kind code	B2
Filing date	Sep 25, 2020
Priority date	Sep 25, 2020
Publication date	Mar 31, 2026
Grant date	Mar 31, 2026

Abstract

Embodiments disclosed herein include complementary metal-oxide-semiconductor (CMOS) devices and methods of making such devices. In an embodiment, a CMOS device comprises a first transistor with a first conductivity type, where the first transistor comprises a first source region and a first drain region, and a first interface material over the first source region and the first drain region. In an embodiment, the CMOS device further comprises a second transistor with a second conductivity type that is opposite form the first conductivity type, where the second transistor comprises a second source region and a second drain region, and a second interface material over the second source region and the second drain region.

First claim

What is claimed is:

1 . A complementary metal-oxide semiconductor (CMOS) device, comprising:
a first transistor with P-type conductivity, wherein the first transistor comprises:
a first source region and a first drain region; and
a first interface material over the first source region and the first drain region; and
a second transistor with N-type conductivity, wherein the second transistor comprises:
a second source region and a second drain region; and
a second interface material over the second source region and the second drain region, wherein the second interface material comprises titanium, and the first interface material does not include titanium.

2 . The CMOS device of claim 1 , wherein the first interface material comprises germanium, and wherein the second interface material comprises TiSi.

3 . The CMOS device of claim 1 , wherein a first thickness of the first interface material is between approximately 1 nm and approximately 10 nm, and wherein a second thickness of the second interface material is between approximately 1 nm and approximately 10 nm.

4 . The CMOS device of claim 3 , wherein the first thickness is substantially equal to the second thickness.

5 . The CMOS device of claim 1 , wherein the first transistor and the second transistor are non-planar devices.

6 . The CMOS device of claim 5 , wherein the non-planar devices are tri-gate devices.

7 . The CMOS device of claim 5 , wherein the non-planar devices are gate-all-around (GAA) devices.

8 . The CMOS device of claim 1 , wherein the first transistor comprises a first number of fins, and wherein the second transistor comprises a second number of fins.

9 . The CMOS device of claim 8 , wherein the second number of fins is greater than the first number of fins.

10 . The CMOS device of claim 1 , wherein the first source region and the first drain region comprise a diamond shaped region.

11 . A complementary metal-oxide-semiconductor (CMOS), comprising:
a first non-planar transistor of P-type conductivity, wherein the first non-planar transistor comprises:
a first fin extending up from a substrate;
a second fin extending up from the substrate;
a first source region connecting the first fin to the second fin;
a first drain region connecting the first fin to the second fin;
a first interface material over the first source region and the first drain region; and
first contacts connected to the first interface material over the first source region and the first drain region; and
a second non-planar transistor of N-type conductivity, wherein the second non-planar transistor comprises:
a third fin extending up from the substrate;
a fourth fin extending up from the substrate;
a fifth fin extending up from the substrate;
a second source region connecting the third fin, the fourth fin, and the fifth fin together;
a second drain region connecting the third fin, the fourth fin, and the fifth fin together;
a second interface material over the second source region and the second drain region, wherein the second interface material comprises titanium, and the first interface material does not include titanium; and
second contacts connected to the first interface material over the second source region and the second drain region.

12 . The CMOS device of claim 11 , wherein the first contacts and the second contacts comprise tungsten.

13 . The CMOS device of claim 11 , wherein the first interface material comprises germanium, and wherein the second interface material comprises TiSi.

14 . The CMOS device of claim 11 , wherein a first thickness of the first interface material is between approximately 1 nm and approximately 10 nm, and wherein a second thickness of the second interface material is between approximately 1 nm and approximately 10 nm.

15 . The CMOS device of claim 14 , wherein the first thickness is substantially equal to the second thickness.

16 . An electronic device, comprising:
a board; a package substrate attached to the board; and a die electrically coupled to the package substrate, wherein the die comprises a complimentary metal-oxide-semiconductor (CMOS) device, wherein the CMOS device comprises:
a first transistor with a first interface material between a first source region and a first contact, the first source region having P-type conductivity; and
a second transistor with a second interface material between a second source region and a second contact, the second source region having N-type conductivity, wherein the second interface material comprises titanium, and the first interface material does not include titanium.

17 . The electronic device of claim 16 , wherein the first transistor is a P-type transistor, and wherein the second transistor is an N-type transistor.

Assignees

• Intel Corp

Inventors

• Cook Kevin
• Murthy Anand S
• Dewey Gilbert
• Haratipour Nazila
• Choi Chi-Hing
• Jha Jitendra Kumar
• Mukherjee Srijit

Classifications

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/0186

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/017 Primary

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title