Semiconductor structure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-12593443-B2
Application number	US-202318149750-A
Country	US
Kind code	B2
Filing date	Jan 4, 2023
Priority date	Apr 29, 2022
Publication date	Mar 31, 2026
Grant date	Mar 31, 2026

Abstract

The present disclosure provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductors. The semiconductor structure includes: a base, where the base includes a memory array region and a peripheral circuit region around the memory array region; a plurality of buried bit lines disposed in the memory array region of the base; and at least one buried gate disposed in the peripheral circuit region of the base.

First claim

The invention claimed is:

1 . A semiconductor structure, comprising:
a base, wherein the base comprises a memory array region and a peripheral circuit region around the memory array region; a plurality of buried bit lines disposed in the memory array region of the base; and at least one buried gate disposed in the peripheral circuit region of the base; wherein the memory array region comprises a plurality of first active regions arranged in an array, at least one of the plurality of buried bit lines penetrates through a column of first active regions.

2 . The semiconductor structure according to claim 1 , wherein bottom surfaces of the plurality of buried bit lines are flush with a bottom surface of the at least one buried gate.

3 . A semiconductor structure, comprising:
a base, wherein the base comprises a memory array region and a peripheral circuit region around the memory array region; a plurality of buried bit lines disposed in the memory array region of the base; and at least one buried gate disposed in the peripheral circuit region of the base; wherein the memory array region comprises a plurality of first active regions arranged in an array, each of the first active regions extends along a first direction, and the plurality of first active regions are isolated by using an isolation structure; the buried bit line comprises a bit line contact structure and a bit line conductive layer that are disposed sequentially; the bit line contact structure is connected to the first active region; and the bit line conductive layer is connected to the bit line contact structure; and the bit line conductive layer extends along a second direction in the memory array region and penetrates through a column of first active regions, and the second direction intersects the first direction non-perpendicularly.

4 . The semiconductor structure according to claim 3 , wherein the buried bit line comprises the bit line conductive layer and a plurality of bit line contact structures connected to the bit line conductive layer, and the plurality of bit line contact structures are arranged in an array and each disposed on the first active region; and
the bit line conductive layer covers top surfaces of a plurality of the bit line contact structures.

5 . The semiconductor structure according to claim 3 , wherein each of the buried bit lines comprises the bit line contact structure and the bit line conductive layer that are stacked sequentially, and the bit line contact structure extends along the second direction.

6 . The semiconductor structure according to claim 3 , wherein the peripheral circuit region comprises a second active region, and the at least one buried gate penetrates through the second active region; and
the buried gate comprises a high-K dielectric layer, a gate contact layer, and a metal gate layer that are disposed sequentially.

7 . The semiconductor structure according to claim 6 , wherein a gate trench is formed in the second active region of the base, the high-K dielectric layer covers a sidewall and a bottom surface of the gate trench, the gate contact layer covers a sidewall and a bottom surface of the high-K dielectric layer, the metal gate layer covers a sidewall and a bottom surface of the gate contact layer, and an upper surface of the metal gate layer is flush with a top surface of the base.

8 . The semiconductor structure according to claim 6 , wherein the bit line contact structure of the buried bit line and the gate contact layer of the buried gate are made of a same contact material layer, and the bit line conductive layer of the buried bit line and the metal gate layer of the buried gate are made of a same metal material layer.

9 . The semiconductor structure according to claim 3 , further comprising:
a plurality of buried word lines disposed in the memory array region, wherein each of the buried word lines extends along a third direction and are located below the plurality of buried bit lines, top surfaces of the plurality of buried word lines are lower than bottom surfaces of the plurality of buried bit lines, and a spacing structure is disposed between the plurality of buried word lines and the plurality of buried bit lines; and the third direction intersects the first direction non-perpendicularly, and the third direction intersects the second direction perpendicularly.

10 . A method of manufacturing a semiconductor structure, comprising:
providing a base, wherein the base comprises a memory array region and a peripheral circuit region around the memory array region; and forming a plurality of buried bit lines in the memory array region, and forming at least one buried gate in the peripheral circuit region; wherein the memory array region comprises a plurality of first active regions arranged in an array, each of the first active regions extends along a first direction, and the plurality of first active regions are isolated by using an isolation structure; the peripheral circuit region comprises a second active region; and the forming a plurality of buried bit lines in the memory array region, and forming at least one buried gate in the peripheral circuit region comprises: forming a plurality of first trenches in the memory array region, wherein the plurality of first trenches are correspondingly arranged in the plurality of first active regions, and forming at least one gate trench in the peripheral circuit region, wherein the at least one gate trench penetrates through the second active region, and bottom surfaces of the plurality of first trenches are flush with a bottom surface of the at least one gate trench; and forming a plurality of second trenches in the memory array region, wherein each of the second trenches extends along a second direction, penetrates through a column of the first active regions, and communicates with the first trench formed in the column of the first active regions, a bottom surface of the second trench is higher than the bottom surface of the first trench, and the second direction intersects the first direction non-perpendicularly.

11 . The method of manufacturing the semiconductor structure according to claim 10 , after the forming at least one gate trench in the peripheral circuit region, comprising:
forming a high-K dielectric layer covering the second active region exposed by the gate trench; forming a bit line contact structure at a bottom of the first trench, and forming a gate contact layer in the gate trench, wherein the gate contact layer covers the high-K dielectric layer; and depositing a metal material, wherein a part of the metal material fills unfilled regions of the first trench and the second trench, to form a bit line conductive layer, and a part of the metal material fills an unfilled region of the gate trench, to form a metal gate layer; and a top surface of the bit line conductive layer is flush with a top surface of the metal gate layer, and the top surface of the bit line conductive layer and the top surface of the metal gate layer are both flush with or below a top surface of the base.

12 . The method of manufacturing the semiconductor structure according to claim 11 , wherein the forming a bit line contact structure at a bottom of the first trench, and forming a gate contact layer in the gate trench comprises:
forming a contact material layer, wherein the contact material layer fills the plurality of first trenches and covers the high-K dielectric layer in the gate trench; and partially removing the contact material layer, wherein the contact material layer retained in the first trench forms the bit line contact structure, and the contact material layer retained in

Assignees

• Changxin Memory Tech Inc
• Changxin Jidian Beijing Memory Tech Co Ltd

Inventors

• Cui Zhaopei
• Song Ying

Classifications

• H10B12/09

  with simultaneous manufacture of the peripheral circuit region and memory cells · CPC title

• H10B12/488

  Word lines · CPC title

• H10B12/50

  Peripheral circuit region structures · CPC title

• H10D30/60

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title

• H10D64/025

  forming recessed gates, e.g. by using local oxidation · CPC title